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Merged
merged 3 commits into from
Jul 11, 2025
Merged

[x86] Synchronize fp128 and i128 ABI tests (nfc) #147923

merged 3 commits into from
Jul 11, 2025

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tgross35
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The ABI tests for fp128 covers a handful of things that the i128 test currently does not, including targets other than x86-64 Linux and some simpler argument cases. Update the i128 test to be consistent with fp128. All existing test function patterns still exist, though they all wind up renamed.

Additionally correct some call signatures in the fp128 test (not relevant for output).

@llvmbot
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llvmbot commented Jul 10, 2025

@llvm/pr-subscribers-backend-x86

Author: Trevor Gross (tgross35)

Changes

The ABI tests for fp128 covers a handful of things that the i128 test currently does not, including targets other than x86-64 Linux and some simpler argument cases. Update the i128 test to be consistent with fp128. All existing test function patterns still exist, though they all wind up renamed.

Additionally correct some call signatures in the fp128 test (not relevant for output).

Patch is 27.82 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/147923.diff

2 Files Affected:

  • (modified) llvm/test/CodeGen/X86/fp128-abi.ll (+6-4)
  • (modified) llvm/test/CodeGen/X86/i128-abi.ll (+642-79)
diff --git a/llvm/test/CodeGen/X86/fp128-abi.ll b/llvm/test/CodeGen/X86/fp128-abi.ll
index 526ed7c72f73f..863ebfc3bd853 100644
--- a/llvm/test/CodeGen/X86/fp128-abi.ll
+++ b/llvm/test/CodeGen/X86/fp128-abi.ll
@@ -1,5 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
+; Consider keeping tests in sync with i128-abi.ll
+
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-X64
 ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-X86
 ; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-MSVC64
@@ -360,7 +362,7 @@ define void @call_first_arg(fp128 %x) nounwind {
 ; CHECK-MINGW-NEXT:    callq first_arg
 ; CHECK-MINGW-NEXT:    addq $56, %rsp
 ; CHECK-MINGW-NEXT:    retq
-  call i128 @first_arg(fp128 %x)
+  call fp128 @first_arg(fp128 %x)
   ret void
 }
 
@@ -452,7 +454,7 @@ define void @call_leading_args(fp128 %x) nounwind {
 ; CHECK-MINGW-NEXT:    callq leading_args
 ; CHECK-MINGW-NEXT:    addq $72, %rsp
 ; CHECK-MINGW-NEXT:    retq
-  call i128 @leading_args(i64 0, i64 0, i64 0, i64 0, fp128 %x)
+  call fp128 @leading_args(i64 0, i64 0, i64 0, i64 0, fp128 %x)
   ret void
 }
 
@@ -562,7 +564,7 @@ define void @call_many_leading_args(fp128 %x) nounwind {
 ; CHECK-MINGW-NEXT:    callq many_leading_args
 ; CHECK-MINGW-NEXT:    addq $88, %rsp
 ; CHECK-MINGW-NEXT:    retq
-  call i128 @many_leading_args(i64 0, i64 0, i64 0, i64 0, fp128 0xL0, fp128 %x)
+  call fp128 @many_leading_args(i64 0, i64 0, i64 0, i64 0, fp128 0xL0, fp128 %x)
   ret void
 }
 
@@ -654,6 +656,6 @@ define void @call_trailing_arg(fp128 %x) nounwind {
 ; CHECK-MINGW-NEXT:    callq trailing_arg
 ; CHECK-MINGW-NEXT:    addq $72, %rsp
 ; CHECK-MINGW-NEXT:    retq
-  call i128 @trailing_arg(i64 0, i64 0, i64 0, i64 0, fp128 %x)
+  call fp128 @trailing_arg(i64 0, i64 0, i64 0, i64 0, fp128 %x)
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/i128-abi.ll b/llvm/test/CodeGen/X86/i128-abi.ll
index 264c546b4cae2..01e2c6dbad227 100644
--- a/llvm/test/CodeGen/X86/i128-abi.ll
+++ b/llvm/test/CodeGen/X86/i128-abi.ll
@@ -1,97 +1,660 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --version 2
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
 
-define i128 @in_reg(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i128 %a4) {
-; CHECK-LABEL: in_reg:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %r9, %rdx
-; CHECK-NEXT:    movq %r8, %rax
-; CHECK-NEXT:    retq
-  ret i128 %a4
+; Consider keeping tests in sync with fp128-abi.ll
+
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-X64
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-X86
+; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-MSVC64
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-MSVC32
+; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-MINGW
+
+define i128 @return(ptr %p) {
+; CHECK-X64-LABEL: return:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq (%rdi), %rax
+; CHECK-X64-NEXT:    movq 8(%rdi), %rdx
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: return:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    pushl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    pushl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-X86-NEXT:    .cfi_offset %esi, -12
+; CHECK-X86-NEXT:    .cfi_offset %edi, -8
+; CHECK-X86-NEXT:    movl 12(%esp), %eax
+; CHECK-X86-NEXT:    movl 16(%esp), %ecx
+; CHECK-X86-NEXT:    movl (%ecx), %edx
+; CHECK-X86-NEXT:    movl 4(%ecx), %esi
+; CHECK-X86-NEXT:    movl 8(%ecx), %edi
+; CHECK-X86-NEXT:    movl 12(%ecx), %ecx
+; CHECK-X86-NEXT:    movl %ecx, 12(%eax)
+; CHECK-X86-NEXT:    movl %edi, 8(%eax)
+; CHECK-X86-NEXT:    movl %esi, 4(%eax)
+; CHECK-X86-NEXT:    movl %edx, (%eax)
+; CHECK-X86-NEXT:    popl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    popl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl $4
+;
+; CHECK-MSVC64-LABEL: return:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    movq (%rcx), %rax
+; CHECK-MSVC64-NEXT:    movq 8(%rcx), %rdx
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: return:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %edi
+; CHECK-MSVC32-NEXT:    pushl %esi
+; CHECK-MSVC32-NEXT:    movl 12(%esp), %eax
+; CHECK-MSVC32-NEXT:    movl 16(%esp), %ecx
+; CHECK-MSVC32-NEXT:    movl (%ecx), %edx
+; CHECK-MSVC32-NEXT:    movl 4(%ecx), %esi
+; CHECK-MSVC32-NEXT:    movl 8(%ecx), %edi
+; CHECK-MSVC32-NEXT:    movl 12(%ecx), %ecx
+; CHECK-MSVC32-NEXT:    movl %ecx, 12(%eax)
+; CHECK-MSVC32-NEXT:    movl %edi, 8(%eax)
+; CHECK-MSVC32-NEXT:    movl %esi, 4(%eax)
+; CHECK-MSVC32-NEXT:    movl %edx, (%eax)
+; CHECK-MSVC32-NEXT:    popl %esi
+; CHECK-MSVC32-NEXT:    popl %edi
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: return:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    movq (%rcx), %rax
+; CHECK-MINGW-NEXT:    movq 8(%rcx), %rdx
+; CHECK-MINGW-NEXT:    retq
+  %r = load i128, ptr %p
+  ret i128 %r
+}
+
+define i128 @first_arg(i128 %x) {
+; CHECK-X64-LABEL: first_arg:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq %rsi, %rdx
+; CHECK-X64-NEXT:    movq %rdi, %rax
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: first_arg:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    pushl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    pushl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-X86-NEXT:    .cfi_offset %esi, -12
+; CHECK-X86-NEXT:    .cfi_offset %edi, -8
+; CHECK-X86-NEXT:    movl 12(%esp), %eax
+; CHECK-X86-NEXT:    movl 16(%esp), %ecx
+; CHECK-X86-NEXT:    movl 20(%esp), %edx
+; CHECK-X86-NEXT:    movl 24(%esp), %esi
+; CHECK-X86-NEXT:    movl 28(%esp), %edi
+; CHECK-X86-NEXT:    movl %edi, 12(%eax)
+; CHECK-X86-NEXT:    movl %esi, 8(%eax)
+; CHECK-X86-NEXT:    movl %edx, 4(%eax)
+; CHECK-X86-NEXT:    movl %ecx, (%eax)
+; CHECK-X86-NEXT:    popl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    popl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl $4
+;
+; CHECK-MSVC64-LABEL: first_arg:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    movq %rcx, %rax
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: first_arg:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %edi
+; CHECK-MSVC32-NEXT:    pushl %esi
+; CHECK-MSVC32-NEXT:    movl 12(%esp), %eax
+; CHECK-MSVC32-NEXT:    movl 16(%esp), %ecx
+; CHECK-MSVC32-NEXT:    movl 20(%esp), %edx
+; CHECK-MSVC32-NEXT:    movl 24(%esp), %esi
+; CHECK-MSVC32-NEXT:    movl 28(%esp), %edi
+; CHECK-MSVC32-NEXT:    movl %edi, 12(%eax)
+; CHECK-MSVC32-NEXT:    movl %esi, 8(%eax)
+; CHECK-MSVC32-NEXT:    movl %edx, 4(%eax)
+; CHECK-MSVC32-NEXT:    movl %ecx, (%eax)
+; CHECK-MSVC32-NEXT:    popl %esi
+; CHECK-MSVC32-NEXT:    popl %edi
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: first_arg:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    movq %rcx, %rax
+; CHECK-MINGW-NEXT:    retq
+  ret i128 %x
 }
 
-define i128 @on_stack(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i128 %a5) {
-; CHECK-LABEL: on_stack:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq 8(%rsp), %rax
-; CHECK-NEXT:    movq 16(%rsp), %rdx
-; CHECK-NEXT:    retq
-  ret i128 %a5
+; Still passed in regs on x86-64
+define i128 @leading_args(i64 %_0, i64 %_1, i64 %_2, i64 %_3, i128 %x) {
+; CHECK-X64-LABEL: leading_args:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq %r9, %rdx
+; CHECK-X64-NEXT:    movq %r8, %rax
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: leading_args:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    pushl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    pushl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-X86-NEXT:    .cfi_offset %esi, -12
+; CHECK-X86-NEXT:    .cfi_offset %edi, -8
+; CHECK-X86-NEXT:    movl 12(%esp), %eax
+; CHECK-X86-NEXT:    movl 48(%esp), %ecx
+; CHECK-X86-NEXT:    movl 52(%esp), %edx
+; CHECK-X86-NEXT:    movl 56(%esp), %esi
+; CHECK-X86-NEXT:    movl 60(%esp), %edi
+; CHECK-X86-NEXT:    movl %edi, 12(%eax)
+; CHECK-X86-NEXT:    movl %esi, 8(%eax)
+; CHECK-X86-NEXT:    movl %edx, 4(%eax)
+; CHECK-X86-NEXT:    movl %ecx, (%eax)
+; CHECK-X86-NEXT:    popl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    popl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl $4
+;
+; CHECK-MSVC64-LABEL: leading_args:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    movq 40(%rsp), %rax
+; CHECK-MSVC64-NEXT:    movq 48(%rsp), %rdx
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: leading_args:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %edi
+; CHECK-MSVC32-NEXT:    pushl %esi
+; CHECK-MSVC32-NEXT:    movl 12(%esp), %eax
+; CHECK-MSVC32-NEXT:    movl 48(%esp), %ecx
+; CHECK-MSVC32-NEXT:    movl 52(%esp), %edx
+; CHECK-MSVC32-NEXT:    movl 56(%esp), %esi
+; CHECK-MSVC32-NEXT:    movl 60(%esp), %edi
+; CHECK-MSVC32-NEXT:    movl %edi, 12(%eax)
+; CHECK-MSVC32-NEXT:    movl %esi, 8(%eax)
+; CHECK-MSVC32-NEXT:    movl %edx, 4(%eax)
+; CHECK-MSVC32-NEXT:    movl %ecx, (%eax)
+; CHECK-MSVC32-NEXT:    popl %esi
+; CHECK-MSVC32-NEXT:    popl %edi
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: leading_args:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    movq 40(%rsp), %rax
+; CHECK-MINGW-NEXT:    movq 48(%rsp), %rdx
+; CHECK-MINGW-NEXT:    retq
+  ret i128 %x
 }
 
-define i128 @on_stack2(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i128 %a5, i128 %a6) {
-; CHECK-LABEL: on_stack2:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq 24(%rsp), %rax
-; CHECK-NEXT:    movq 32(%rsp), %rdx
-; CHECK-NEXT:    retq
-  ret i128 %a6
+; No longer in args on any platform
+define i128 @many_leading_args(i64 %_0, i64 %_1, i64 %_2, i64 %_3, i64 %_4, i128 %_5, i128 %x) {
+; CHECK-X64-LABEL: many_leading_args:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq 24(%rsp), %rax
+; CHECK-X64-NEXT:    movq 32(%rsp), %rdx
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: many_leading_args:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    pushl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    pushl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-X86-NEXT:    .cfi_offset %esi, -12
+; CHECK-X86-NEXT:    .cfi_offset %edi, -8
+; CHECK-X86-NEXT:    movl 12(%esp), %eax
+; CHECK-X86-NEXT:    movl 72(%esp), %ecx
+; CHECK-X86-NEXT:    movl 76(%esp), %edx
+; CHECK-X86-NEXT:    movl 80(%esp), %esi
+; CHECK-X86-NEXT:    movl 84(%esp), %edi
+; CHECK-X86-NEXT:    movl %edi, 12(%eax)
+; CHECK-X86-NEXT:    movl %esi, 8(%eax)
+; CHECK-X86-NEXT:    movl %edx, 4(%eax)
+; CHECK-X86-NEXT:    movl %ecx, (%eax)
+; CHECK-X86-NEXT:    popl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    popl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl $4
+;
+; CHECK-MSVC64-LABEL: many_leading_args:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    movq 64(%rsp), %rax
+; CHECK-MSVC64-NEXT:    movq 72(%rsp), %rdx
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: many_leading_args:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %edi
+; CHECK-MSVC32-NEXT:    pushl %esi
+; CHECK-MSVC32-NEXT:    movl 12(%esp), %eax
+; CHECK-MSVC32-NEXT:    movl 72(%esp), %ecx
+; CHECK-MSVC32-NEXT:    movl 76(%esp), %edx
+; CHECK-MSVC32-NEXT:    movl 80(%esp), %esi
+; CHECK-MSVC32-NEXT:    movl 84(%esp), %edi
+; CHECK-MSVC32-NEXT:    movl %edi, 12(%eax)
+; CHECK-MSVC32-NEXT:    movl %esi, 8(%eax)
+; CHECK-MSVC32-NEXT:    movl %edx, 4(%eax)
+; CHECK-MSVC32-NEXT:    movl %ecx, (%eax)
+; CHECK-MSVC32-NEXT:    popl %esi
+; CHECK-MSVC32-NEXT:    popl %edi
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: many_leading_args:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    movq 64(%rsp), %rax
+; CHECK-MINGW-NEXT:    movq 72(%rsp), %rdx
+; CHECK-MINGW-NEXT:    retq
+  ret i128 %x
 }
 
-define i64 @trailing_arg_on_stack(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i128 %a5, i64 %a6) {
-; CHECK-LABEL: trailing_arg_on_stack:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %r9, %rax
-; CHECK-NEXT:    retq
-  ret i64 %a6
+define i128 @trailing_arg(i64 %_0, i64 %_1, i64 %_2, i64 %_3, i64 %_4, i128 %x, i64 %_5) {
+; CHECK-X64-LABEL: trailing_arg:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq 8(%rsp), %rax
+; CHECK-X64-NEXT:    movq 16(%rsp), %rdx
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: trailing_arg:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    pushl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    pushl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-X86-NEXT:    .cfi_offset %esi, -12
+; CHECK-X86-NEXT:    .cfi_offset %edi, -8
+; CHECK-X86-NEXT:    movl 12(%esp), %eax
+; CHECK-X86-NEXT:    movl 56(%esp), %ecx
+; CHECK-X86-NEXT:    movl 60(%esp), %edx
+; CHECK-X86-NEXT:    movl 64(%esp), %esi
+; CHECK-X86-NEXT:    movl 68(%esp), %edi
+; CHECK-X86-NEXT:    movl %edi, 12(%eax)
+; CHECK-X86-NEXT:    movl %esi, 8(%eax)
+; CHECK-X86-NEXT:    movl %edx, 4(%eax)
+; CHECK-X86-NEXT:    movl %ecx, (%eax)
+; CHECK-X86-NEXT:    popl %esi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X86-NEXT:    popl %edi
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl $4
+;
+; CHECK-MSVC64-LABEL: trailing_arg:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    movq 48(%rsp), %rax
+; CHECK-MSVC64-NEXT:    movq 56(%rsp), %rdx
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: trailing_arg:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %edi
+; CHECK-MSVC32-NEXT:    pushl %esi
+; CHECK-MSVC32-NEXT:    movl 12(%esp), %eax
+; CHECK-MSVC32-NEXT:    movl 56(%esp), %ecx
+; CHECK-MSVC32-NEXT:    movl 60(%esp), %edx
+; CHECK-MSVC32-NEXT:    movl 64(%esp), %esi
+; CHECK-MSVC32-NEXT:    movl 68(%esp), %edi
+; CHECK-MSVC32-NEXT:    movl %edi, 12(%eax)
+; CHECK-MSVC32-NEXT:    movl %esi, 8(%eax)
+; CHECK-MSVC32-NEXT:    movl %edx, 4(%eax)
+; CHECK-MSVC32-NEXT:    movl %ecx, (%eax)
+; CHECK-MSVC32-NEXT:    popl %esi
+; CHECK-MSVC32-NEXT:    popl %edi
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: trailing_arg:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    movq 48(%rsp), %rax
+; CHECK-MINGW-NEXT:    movq 56(%rsp), %rdx
+; CHECK-MINGW-NEXT:    retq
+  ret i128 %x
+}
+
+define void @call_first_arg(i128 %x) nounwind {
+; CHECK-X64-LABEL: call_first_arg:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    pushq %rax
+; CHECK-X64-NEXT:    callq first_arg@PLT
+; CHECK-X64-NEXT:    popq %rax
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: call_first_arg:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    subl $40, %esp
+; CHECK-X86-NEXT:    leal 12(%esp), %eax
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl %eax
+; CHECK-X86-NEXT:    calll first_arg@PLT
+; CHECK-X86-NEXT:    addl $56, %esp
+; CHECK-X86-NEXT:    retl
+;
+; CHECK-MSVC64-LABEL: call_first_arg:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    subq $40, %rsp
+; CHECK-MSVC64-NEXT:    callq first_arg
+; CHECK-MSVC64-NEXT:    addq $40, %rsp
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: call_first_arg:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %ebp
+; CHECK-MSVC32-NEXT:    movl %esp, %ebp
+; CHECK-MSVC32-NEXT:    andl $-16, %esp
+; CHECK-MSVC32-NEXT:    subl $32, %esp
+; CHECK-MSVC32-NEXT:    movl %esp, %eax
+; CHECK-MSVC32-NEXT:    pushl 20(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 16(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 12(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 8(%ebp)
+; CHECK-MSVC32-NEXT:    pushl %eax
+; CHECK-MSVC32-NEXT:    calll _first_arg
+; CHECK-MSVC32-NEXT:    addl $20, %esp
+; CHECK-MSVC32-NEXT:    movl %ebp, %esp
+; CHECK-MSVC32-NEXT:    popl %ebp
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: call_first_arg:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    subq $40, %rsp
+; CHECK-MINGW-NEXT:    callq first_arg
+; CHECK-MINGW-NEXT:    addq $40, %rsp
+; CHECK-MINGW-NEXT:    retq
+  call i128 @first_arg(i128 %x)
+  ret void
 }
 
-define void @call_in_reg(i128 %x) nounwind {
-; CHECK-LABEL: call_in_reg:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    movq %rsi, %r9
-; CHECK-NEXT:    movq %rdi, %r8
-; CHECK-NEXT:    movl $1, %esi
-; CHECK-NEXT:    movl $2, %edx
-; CHECK-NEXT:    movl $3, %ecx
-; CHECK-NEXT:    xorl %edi, %edi
-; CHECK-NEXT:    callq in_reg@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  call i128 @in_reg(i64 0, i64 1, i64 2, i64 3, i128 %x)
+define void @call_leading_args(i128 %x) nounwind {
+; CHECK-X64-LABEL: call_leading_args:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    pushq %rax
+; CHECK-X64-NEXT:    movq %rsi, %r9
+; CHECK-X64-NEXT:    movq %rdi, %r8
+; CHECK-X64-NEXT:    xorl %edi, %edi
+; CHECK-X64-NEXT:    xorl %esi, %esi
+; CHECK-X64-NEXT:    xorl %edx, %edx
+; CHECK-X64-NEXT:    xorl %ecx, %ecx
+; CHECK-X64-NEXT:    callq leading_args@PLT
+; CHECK-X64-NEXT:    popq %rax
+; CHECK-X64-NEXT:    retq
+;
+; CHECK-X86-LABEL: call_leading_args:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    subl $40, %esp
+; CHECK-X86-NEXT:    leal 12(%esp), %eax
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl 56(%esp)
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl $0
+; CHECK-X86-NEXT:    pushl %eax
+; CHECK-X86-NEXT:    calll leading_args@PLT
+; CHECK-X86-NEXT:    addl $88, %esp
+; CHECK-X86-NEXT:    retl
+;
+; CHECK-MSVC64-LABEL: call_leading_args:
+; CHECK-MSVC64:       # %bb.0:
+; CHECK-MSVC64-NEXT:    subq $56, %rsp
+; CHECK-MSVC64-NEXT:    movq %rdx, 40(%rsp)
+; CHECK-MSVC64-NEXT:    movq %rcx, 32(%rsp)
+; CHECK-MSVC64-NEXT:    xorl %ecx, %ecx
+; CHECK-MSVC64-NEXT:    xorl %edx, %edx
+; CHECK-MSVC64-NEXT:    xorl %r8d, %r8d
+; CHECK-MSVC64-NEXT:    xorl %r9d, %r9d
+; CHECK-MSVC64-NEXT:    callq leading_args
+; CHECK-MSVC64-NEXT:    addq $56, %rsp
+; CHECK-MSVC64-NEXT:    retq
+;
+; CHECK-MSVC32-LABEL: call_leading_args:
+; CHECK-MSVC32:       # %bb.0:
+; CHECK-MSVC32-NEXT:    pushl %ebp
+; CHECK-MSVC32-NEXT:    movl %esp, %ebp
+; CHECK-MSVC32-NEXT:    andl $-16, %esp
+; CHECK-MSVC32-NEXT:    subl $32, %esp
+; CHECK-MSVC32-NEXT:    movl %esp, %eax
+; CHECK-MSVC32-NEXT:    pushl 20(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 16(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 12(%ebp)
+; CHECK-MSVC32-NEXT:    pushl 8(%ebp)
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl $0
+; CHECK-MSVC32-NEXT:    pushl %eax
+; CHECK-MSVC32-NEXT:    calll _leading_args
+; CHECK-MSVC32-NEXT:    addl $52, %esp
+; CHECK-MSVC32-NEXT:    movl %ebp, %esp
+; CHECK-MSVC32-NEXT:    popl %ebp
+; CHECK-MSVC32-NEXT:    retl
+;
+; CHECK-MINGW-LABEL: call_leading_args:
+; CHECK-MINGW:       # %bb.0:
+; CHECK-MINGW-NEXT:    subq $56, %rsp
+; CHECK-MINGW-NEXT:    movq %rdx, 40(%rsp)
+; CHECK-MINGW-NEXT:    movq %rcx, 32(%rsp)
+; CHECK-MINGW-NEXT:    xorl %ecx, %ecx
+; CHECK-MINGW-NEXT:    xorl %edx, %edx
+; CHECK-MINGW-NEXT:    xorl %r8d, %r8d
+; CHECK-MINGW-NEXT:    xorl %r9d, %r9d
+; CHECK-MINGW-NEXT:    callq leading_args
+; CHECK-MINGW-NEXT:    addq $56, %rsp
+; CHECK-MINGW-NEXT:    retq
+  call i128 @leading_args(i64 0, i64 0, i64 0, i64 0, i128 %x)
   ret void
 }
 
-define void @call_on_stack(i128 %x) nounwind {
-; CHECK-LABEL: call_on_stack:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    movq %rdi, %r9
-; CHECK-NEXT:    movl $1, %esi
-; CHECK-NEXT:    movl $2, %edx
-; CHECK-NEXT:...
[truncated]

@tgross35
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I'm working on some fixes for the fp128/i128 ABI, updating the test here to show current behavior.

@RKSimon RKSimon requested review from RKSimon and phoebewang July 10, 2025 09:29
@phoebewang
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How about replace the type in the RUN command, so that we can share the same source and probably same CHECK when you fixed it. An example in llvm/test/CodeGen/X86/vector-lrint-f16.ll

@tgross35
[x86] Rename the fp128 ABI test to i128-fp128-abi (nfc)
77ea75f 
This test will be updated to cover both fp128 and i128. Do the rename in
a separate commit to avoid confusing git's similarity index.
@tgross35
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Great idea, did what you suggested and it's pretty clean. A second sed was needed to use either 0xL0 or 0 for a literal zero, not sure if there is something better to do here.

Renamed the file in the first commit so git history correctly reflects that the file is modified rather than deleted+re-added. If that's important, the first commit will need to be pushed before this PR merges.

@tgross35
[x86] Combine fp128 and i128 ABI tests (nfc)
934f505 
The ABI tests for fp128 covers a handful of things that the i128 test
currently does not, including targets other than x86-64 Linux and some
simpler argument cases. Since these tests should test the same
function patterns, and since some of the directives can be reused,
combine `fp128-abi.ll` and `i128-abi.ll` into one test using `sed` to
set the type.
phoebewang
phoebewang approved these changes Jul 11, 2025
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LGTM with one nit.

llvm/test/CodeGen/X86/i128-fp128-abi.ll Outdated
; CHECK-X86-LABEL: return:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: pushl %edi
; CHECK-X86-NEXT: .cfi_def_cfa_offset 8
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Add nounwind to remove such directives.

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Thanks, added the nounwinds.

I'll need you to land this for me (note the git quirk at #147923 (comment))

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We use "Squash and merge" button. Intermediate commits will not be preserved.

@phoebewang phoebewang merged commit 22d584e into llvm:main Jul 11, 2025
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@tgross35 tgross35 deleted the i128-abi-test branch July 11, 2025 04:19
@tgross35 tgross35 mentioned this pull request Aug 12, 2025
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@phoebewang phoebewang phoebewang approved these changes

@RKSimon RKSimon Awaiting requested review from RKSimon

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@tgross35 @llvmbot @phoebewang