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1 change: 1 addition & 0 deletions src/coreclr/jit/codegencommon.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,7 @@ CodeGen::CodeGen(Compiler* theCompiler) : CodeGenInterface(theCompiler)
negBitmaskDbl = nullptr;
absBitmaskFlt = nullptr;
absBitmaskDbl = nullptr;
zroSimd12Elm3 = nullptr;
u8ToDblBitmask = nullptr;
#endif // defined(TARGET_XARCH)

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2 changes: 1 addition & 1 deletion src/coreclr/jit/simdcodegenxarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -548,7 +548,7 @@ void CodeGen::genSimd12UpperClear(regNumber tgtReg)
zroSimd12Elm3 = GetEmitter()->emitSimd16Const(constValue);
}

GetEmitter()->emitIns_SIMD_R_R_C(INS_andpd, EA_16BYTE, tgtReg, tgtReg, zroSimd12Elm3, 0);
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andpd vs andps doesn't matter, but it should've been andps since that's "more correct" for TYP_SIMD12 (e.g. Vector3 where all fields are float).

GetEmitter()->emitIns_SIMD_R_R_C(INS_andps, EA_16BYTE, tgtReg, tgtReg, zroSimd12Elm3, 0);
}
}

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