An abstraction library for interfacing EDA tools

Repurposing existing HDL tools to help writing better code

A Python package to use FPGA development tools programmatically.

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

A meta repo with numerous different templates or boilerplate projects for several languages and technologies.

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project