Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Verilog AHB Bus implementation for VAAMAN

This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

Popular bus implementations in Verilog HDL

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

This repository contains the source code and results for AMBA AHB to APB Bridge design performing single read, single write and burst write transfers. The design is coded in Verilog, using Modelsim simulator and synthesized using Quartus Prime software.

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Single Master Multiple Slave AHB protocol is carried out. Necessary images of architecture used are also attached. Pls check them out!