Add Zephyr support for Mediatek MT8365 platform

app/boards/mt8365_mt8365_adsp.conf

@@ -0,0 +1,10 @@
+# Boilerplate.  Because the "Platform" is a kconfig "choice" (of which
+# "MTK" is an member), it can't be selected automatically from other
+# kconfigs, nor expressed as a default.  Don't put anything else here.
+# Board-level config goes in Zephyr (and ideally in DTS).  App-level
+# config goes in prj.conf.
+CONFIG_MTK=y
+
+# Override project default setting so 1 millisecond is exactly
+# represented by an integral number of ticks.
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=13000

scripts/xtensa-build-zephyr.py

@@ -145,6 +145,11 @@ class PlatformConfig:
 		f"RJ-2024.3{xtensa_tools_version_postfix}",
 		"HiFi5_MPU_lock_2023_11",
 	),
+	"mt8365" : PlatformConfig(
+		"mtk", "mt8365/mt8365/adsp",
+		f"RJ-2024.3{xtensa_tools_version_postfix}",
+		"hifi4_Aquila_E2_PROD",
+	),
 }
 
 # These can all be built out of the box. --all builds all these.
@@ -1288,7 +1293,7 @@ def gzip_compress(fname, gzdst=None):
 
 RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8ulp', 'imx95']
 RI_INFO_UNSUPPORTED += ['rn', 'acp_6_0']
-RI_INFO_UNSUPPORTED += ['mt8186', 'mt8188', 'mt8195', 'mt8196']
+RI_INFO_UNSUPPORTED += ['mt8186', 'mt8188', 'mt8195', 'mt8196', 'mt8365']
 
 # For temporary workarounds. Unlike _UNSUPPORTED above, the platforms below will print a warning.
 RI_INFO_FIXME = [ ]

src/platform/mtk/dai.c

@@ -22,6 +22,9 @@
 #elif defined(CONFIG_SOC_MT8196)
 #define MTK_AFE_BASE 0x1a110000
 #define SRAM_CPU_START 0x1a210000
+#elif defined(CONFIG_SOC_MT8365)
+#define MTK_AFE_BASE 0x11220000
+#define SRAM_CPU_START 0x1e000000
 #else
 #error Unrecognized device
 #endif
@@ -133,7 +136,7 @@ static void cfg_convert(const struct afe_cfg *src, struct mtk_base_memif_data *d
 	.base = DT_PROP(n, base), \
 	.end = DT_PROP(n, end), \
 	.cur = DT_PROP(n, cur), \
-	.fs = DT_PROP(n, fs), \
+	COND_PROP(n, fs) \
 	.hd = DT_PROP(n, hd), \
 	.enable = DT_PROP(n, enable), \
 	COND_PROP(n, mono) \
@@ -269,6 +272,20 @@ static unsigned int mtk_afe_fs_timing(unsigned int rate)
 		{ 192000, 14 },
 		{ 352800,  7 },
 		{ 384000,  3 },
+#elif defined(CONFIG_SOC_MT8365)
+		{   8000,  0 },
+		{  11025,  1 },
+		{  12000,  2 },
+		{  16000,  4 },
+		{  22050,  5 },
+		{  24000,  6 },
+		{  32000,  8 },
+		{  44100,  9 },
+		{  48000, 10 },
+		{  88200, 11 },
+		{  96000, 12 },
+		{ 176400, 13 },
+		{ 192000, 14 },
 #else
 		{   8000,  0 },
 		{  11025,  1 },

src/platform/mtk/include/platform/lib/memory.h

@@ -42,7 +42,7 @@ static inline void *platform_shared_get(void *ptr, int bytes)
  * validation that the kernel driver interprets the manifest
  * correctly.  Right now we're using the historical addresses.
  */
-#ifdef CONFIG_SOC_MT8195
+#if defined(CONFIG_SOC_MT8195) || defined(CONFIG_SOC_MT8365)
 #define MTK_IPC_BASE (DT_REG_ADDR(DT_NODELABEL(dram0)) + 0x800000)
 #else
 #define MTK_IPC_BASE (DT_REG_ADDR(DT_NODELABEL(dram0)) + 0x500000)

src/platform/mtk/platform.c

@@ -24,12 +24,25 @@
 
 void mtk_dai_init(struct sof *sof);
 
+#ifndef CONFIG_SOC_MT8365
 #define MBOX0 DEVICE_DT_GET(DT_INST(0, mediatek_mbox))
 #define MBOX1 DEVICE_DT_GET(DT_INST(1, mediatek_mbox))
+#else
+#define IPI DEVICE_DT_GET(DT_INST(0, mediatek_ipi))
+
+#define MAILBOX_DEBUG_BASE MTK_IPC_WIN_BASE(DEBUG)
+
+#define SRAM_REG_OP_CPU2DSP		0x8
+#define SRAM_REG_OP_DSP2CPU		0xC
+
+#define ADSP_IPI_OP_REQ		0x1
+#define ADSP_IPI_OP_RSP		0x2
+#endif
 
 /* Use the same UUID as in "ipc-zephyr.c", which is actually an Intel driver */
 SOF_DEFINE_REG_UUID(zipc_task);
 
+#ifndef CONFIG_SOC_MT8365
 static void mbox_cmd_fn(const struct device *mbox, void *arg)
 {
 	/* We're in ISR context.  This unblocks the IPC task thread,
@@ -38,6 +51,7 @@ static void mbox_cmd_fn(const struct device *mbox, void *arg)
 	 */
 	ipc_schedule_process(ipc_get());
 }
+#endif
 
 enum task_state ipc_platform_do_cmd(struct ipc *ipc)
 {
@@ -54,13 +68,23 @@ enum task_state ipc_platform_do_cmd(struct ipc *ipc)
 
 void ipc_platform_complete_cmd(struct ipc *ipc)
 {
+#ifndef CONFIG_SOC_MT8365
 	mtk_adsp_mbox_signal(MBOX0, 1);
+#else
+	*(uint32_t *)(MAILBOX_DEBUG_BASE + SRAM_REG_OP_DSP2CPU) = ADSP_IPI_OP_RSP;
+	mtk_adsp_ipi_signal(IPI, 1);
+#endif
 }
 
 static void mtk_ipc_send(const void *msg, size_t sz)
 {
 	mailbox_dspbox_write(0, msg, sz);
+#ifndef CONFIG_SOC_MT8365
 	mtk_adsp_mbox_signal(MBOX1, 0);
+#else
+	*(uint32_t *)(MAILBOX_DEBUG_BASE + SRAM_REG_OP_DSP2CPU) = ADSP_IPI_OP_REQ;
+	mtk_adsp_ipi_signal(IPI, 1);
+#endif
 }
 
 int ipc_platform_send_msg(const struct ipc_msg *msg)
@@ -75,11 +99,36 @@ int ipc_platform_send_msg(const struct ipc_msg *msg)
 	return 0;
 }
 
+#ifndef CONFIG_SOC_MT8365
 static void mbox_reply_fn(const struct device *mbox, void *arg)
 {
 	ipc_get()->is_notification_pending = false;
 }
 
+#else
+
+static void ipi_handler_fn(const struct device *ipi, void *arg)
+{
+	uint32_t op;
+
+	op = *(uint32_t *)(MAILBOX_DEBUG_BASE + SRAM_REG_OP_CPU2DSP);
+
+	switch (op) {
+	case ADSP_IPI_OP_REQ:
+		/* new message from host */
+		ipc_schedule_process(ipc_get());
+		break;
+	case ADSP_IPI_OP_RSP:
+		/* reply message(done) from host */
+		ipc_get()->is_notification_pending = false;
+		break;
+	default:
+		/* do nothing */
+		break;
+	}
+}
+#endif
+
 /* "Host Page Table" support.  The platform is responsible for
  * providing a buffer into which the IPC layer reads a DMA "page
  * table" from the host.  This isn't really a page table, it's a
@@ -114,8 +163,12 @@ int platform_ipc_init(struct ipc *ipc)
 	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(zipc_task_uuid),
 			       &ipc_task_ops, ipc, 0, 0);
 
+#ifndef CONFIG_SOC_MT8365
 	mtk_adsp_mbox_set_handler(MBOX0, 0, mbox_cmd_fn, NULL);
 	mtk_adsp_mbox_set_handler(MBOX1, 1, mbox_reply_fn, NULL);
+#else
+	mtk_adsp_ipi_set_handler(IPI, 0, ipi_handler_fn, NULL);
+#endif
 	return 0;
 }
 

zephyr/lib/alloc.c

@@ -120,10 +120,17 @@ char __aligned(8) heapmem[HEAPMEM_SIZE];
 #elif defined(CONFIG_SOC_FAMILY_MTK)
 
 extern char _mtk_adsp_sram_end;
+#if defined(CONFIG_SOC_MT8365)
+#define SRAM_START DT_REG_ADDR(DT_NODELABEL(sram1))
+#define SRAM_SIZE  DT_REG_SIZE(DT_NODELABEL(sram1))
+#define heapmem ((uint8_t *)SRAM_START)
+#else
 #define SRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
 #define SRAM_SIZE  DT_REG_SIZE(DT_NODELABEL(sram0))
-#define SRAM_END   (SRAM_START + SRAM_SIZE)
 #define heapmem ((uint8_t *)ALIGN_UP((uintptr_t)&_mtk_adsp_sram_end, PLATFORM_DCACHE_ALIGN))
+#endif /* CONFIG_SOC_MT8365 */
+
+#define SRAM_END   (SRAM_START + SRAM_SIZE)
 
 /* Heap size is limited to 0x7fffU chunk units when CONFIG_SYS_HEAP_SMALL_ONLY is set */
 #if defined(CONFIG_SYS_HEAP_SMALL_ONLY)