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Rancid(0)'s 4.14.14 fixes and clean-up #1

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Merged
merged 1 commit into from
Mar 21, 2022
Merged

Rancid(0)'s 4.14.14 fixes and clean-up #1

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1 change: 1 addition & 0 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1383,6 +1383,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_LIVERPOOL:
#endif
default:
return 0;
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6 changes: 3 additions & 3 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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Expand Up @@ -168,7 +168,6 @@ module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);

MODULE_PARM_DESC(abort_on_lockup, "Abort GPU jobs on after a GPU lockup (1 = enable, 0 = disable (default))");
module_param_named(abort_on_lockup, amdgpu_abort_on_lockup, int, 0644);

MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(dpm, amdgpu_dpm, int, 0444);

Expand Down Expand Up @@ -459,7 +458,8 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
/* liverpool */
{0x1002, 0x9920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},

{0x1002, 0x9923, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
{0x1002, 0x9924, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
#endif
/* topaz */
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
Expand Down Expand Up @@ -586,7 +586,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
ret = amdgpu_kick_out_firmware_fb(pdev);
if (ret)
return ret;

#ifdef CONFIG_X86_PS4
/* On the PS4 (Liverpool graphics) we have a hard dependency on the
* Aeolia driver to set up the HDMI encoder which is connected to it,
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
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Expand Up @@ -92,7 +92,6 @@ MODULE_FIRMWARE("radeon/liverpool_ce.bin");
MODULE_FIRMWARE("radeon/liverpool_rlc.bin");
MODULE_FIRMWARE("radeon/liverpool_mec.bin");
MODULE_FIRMWARE("radeon/liverpool_mec2.bin");

static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
{
{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
Expand Down Expand Up @@ -5157,6 +5156,7 @@ static int gfx_v7_0_sw_init(void *handle)
case CHIP_HAWAII:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_LIVERPOOL:
default:
adev->gfx.mec.num_mec = 1;
break;
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6 changes: 0 additions & 6 deletions drivers/gpu/drm/radeon/radeon_asic.c
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Expand Up @@ -2248,12 +2248,6 @@ static struct radeon_asic kv_asic = {
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
.copy = &cik_copy_dma,
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
// .blit = &cik_copy_cpdma,
// .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
// .dma = &cik_copy_cpdma,
// .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
// .copy = &cik_copy_cpdma,
// .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
.surface = {
.set_reg = r600_set_surface_reg,
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