`riscv-rt`: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)

[hegza]

The RAM init function is incompatible with (as of yet, unratified) RV32E base ISA.

riscv/riscv-rt/src/asm.rs

Lines 147 to 158 in f5a2da9

	// Copy .data from flash to RAM
	la t0, _sdata
	la t2, _edata
	la t1, _sidata
	bgeu t0, t2, 2f
	1: ",
	#[cfg(target_arch = "riscv32")]
	"lw t3, 0(t1)
	addi t1, t1, 4
	sw t3, 0(t0)
	addi t0, t0, 4
	bltu t0, t2, 1b",

The algorithm uses temporaries t0--t3 to copy data from from flash to RAM. However, the RV32E removes registers x16--x31, which includes t3 / x28, therefore making this algorithm unavailable on RVE.

Proposals for a solution

1. We could pick another register in range x0--x16 in place of t3 to make the code compatible between RVI and RVE
2. We could #[cfg(riscve)] the algorithm to use another register on RV32E.

[romancardenas]

I personally prefer using another register that fits all the specifications

[romancardenas]

Solved in #243