[TB] poll debug module's SBCS register and clear errors in status reg check #47
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This fixes a potential bug:
TCDM reads issued by the debug module may take so long to get filled that the JTAG request to read out the result of the memory read comes too early. In this case, the debug module sets an internal error flag which prevents it from issuing any more TCDM transactions. By periodically clearing this error flag in the testbench while checking the core status register, we make sure that tests terminate correctly.