Add support for preloading #104
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…TL sim
The correct generation of preloaded data depends on a mem.json file that
is located inside the ROOT/sim folder of each given PULP chip, and describes
the memory architecture.
For example, the typical architecture of a PULPissimo SoC with 32+32 KiB of
private L2 and 448 KiB of shared L2 divided in 4 word-interleaved banks is
described as follows:
```
{
"pri0": {
"base" : "0x1c000000",
"length" : "32768",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/bank_sram_pri0_i/sram",
"interleaving": "None"
},
"pri1": {
"base" : "0x1c008000",
"length" : "32768",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/bank_sram_pri1_i/sram",
"interleaving": "None"
},
"l2_0": {
"base" : "0x1c010000",
"length" : "458752",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/CUTS[0]/bank_i/sram",
"interleaving": "4",
"interleaving_bank": "0"
},
"l2_1": {
"base" : "0x1c010000",
"length" : "458752",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/CUTS[1]/bank_i/sram",
"interleaving": "4",
"interleaving_bank": "1"
},
"l2_2": {
"base" : "0x1c010000",
"length" : "458752",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/CUTS[2]/bank_i/sram",
"interleaving": "4",
"interleaving_bank": "2"
},
"l2_3": {
"base" : "0x1c010000",
"length" : "458752",
"instance": "/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/CUTS[3]/bank_i/sram",
"interleaving": "4",
"interleaving_bank": "3"
}
}
```
The SDK will automatically generate one file for each JSON dictionary
entry inside `vectors`, but keep the JTAG loading method by default.
To switch to preloading, one can set the `bootmode` env variable
on the fly while calling the Make command:
```
make all run platform=rtl bootmode=preload
```
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Add (back) support for preloading L2 and L1 memory in RTL simulations. The "best" option might be to rely on information directly in the SDK, but in this PR instead the strategy is to rely on an external
mem.jsonfile distributed together with the PULP RTL, inside the ROOT/sim folder of each given PULP chip, to describe the memory architecture.For example, the typical architecture of a PULPissimo SoC with 32+32 KiB of private L2 and 448 KiB of shared L2 divided in 4 word-interleaved banks is described as follows:
The SDK will automatically generate one file for each JSON dictionary entry inside
vectors, but keep the JTAG loading method by default. To switch to preloading, one can set thebootmodeenv variable on the fly while calling the Make command: