[Intel-SIG] 5.15 - CWF PMU support for uncore and event #81
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commit 24d74b9 upstream. AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 4] AVX-VNNI-INT8 is on a new and sparse CPUID leaf and all bits on this leaf have no truly kernel use case for now. Given that and to save space for kernel feature bits, move this new leaf to KVM-only subleaf and plus an x86_FEATURE definition for AVX-VNNI-INT8 to direct it to the KVM entry. Advertise AVX-VNNI-INT8 to KVM userspace. This is safe because there are no new VMX controls or additional host enabling required for guests to use this feature. Intel-SIG: commit 24d74b9 KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space. ClearWater support including CPU model and new ISAs and its dependency Signed-off-by: Jiaxi Chen <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 090e3be upstream. Server product based on the Atom Darkmont core. Intel-SIG: commit 090e3be x86/cpu: Add model number for Intel Clearwater Forest processor. ClearWater support including CPU model and new ISAs and its dependency Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit a0423af92cb31e6fc4f53ef9b6e19fdf08ad4395 upstream. Latest Intel platform Clearwater Forest has introduced new instructions enumerated by CPUIDs of SHA512, SM3, SM4 and AVX-VNNI-INT16. Advertise these CPUIDs to userspace so that guests can query them directly. SHA512, SM3 and SM4 are on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering they have not truly kernel usages, hide them in /proc/cpuinfo. These new instructions only operate in xmm, ymm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising these CPUIDs to userspace is safe. Intel-SIG: commit a0423af92cb3 x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest. ClearWater support including CPU model and new ISAs and its dependency Tested-by: Jiaan Lu <[email protected]> Tested-by: Xuelian Guo <[email protected]> Signed-off-by: Tao Su <[email protected]> Message-ID: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 8a8a9c9 upstream. This one is the regular laptop CPU. Intel-SIG: commit 8a8a9c9 x86/cpu: Add model number for another Intel Arrow Lake mobile processor. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit a9d0adc upstream. Refactor struct cpuinfo_x86 so that the vendor, family, and model fields are overlaid in a union with a 32-bit field that combines all three (together with a one byte reserved field in the upper byte). This will make it easy, cheap, and reliable to check all three values at once. See https://lore.kernel.org/r/Zgr6kT8oULbnmEXx@agluck-desk3 for why the ordering is (low-to-high bits): (vendor, family, model) [ bp: Move comments over the line, add the backstory about the particular order of the fields. ] Intel-SIG: commit a9d0adc x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit e6dfdc2 upstream. To avoid adding a slew of new macros for each new Intel CPU family switch over from providing CPU model number #defines to a new scheme that encodes vendor, family, and model in a single number. [ bp: s/casted/cast/g ] Intel-SIG: commit e6dfdc2 x86/cpu/vfm: Add new macros to work with (vendor/family/model) values. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit f055b62 upstream. New CPU #defines encode vendor and family as well as model. Update the example usage comment in arch/x86/kernel/cpu/match.c Intel-SIG: commit f055b62 x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 744866f upstream. New CPU #defines encode vendor and family as well as model. Update INTEL_CPU_DESC() to work with vendor/family/model. Intel-SIG: commit 744866f x86/cpu: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-34-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6568fc1 upstream. New CPU #defines encode vendor and family as well as model. Intel-SIG: commit 6568fc1 x86/cpu/intel: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-29-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 34b3fc5 upstream. The outer if () should have been dropped when switching to c->x86_vfm. Fixes: 6568fc1 ("x86/cpu/intel: Switch to new Intel CPU model defines") Intel-SIG: commit 34b3fc5 x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Andrew Cooper <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Acked-by: Tony Luck <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit d142df1 upstream. New CPU #defines encode vendor and family as well as model. Intel-SIG: commit d142df1 perf/x86/intel: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-32-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 3f710be02ea648001ba18fb2c9fa7765e743dec2 upstream. The below warning may be triggered on GNR when the PCIE uncore units are exposed. WARNING: CPU: 4 PID: 1 at arch/x86/events/intel/uncore.c:1169 uncore_pci_pmu_register+0x158/0x190 The current uncore driver assumes that all the devices in the same PMU have the exact same devfn. It's true for the previous platforms. But it doesn't work for the new PCIE uncore units on GNR. The assumption doesn't make sense. There is no reason to limit the devices from the same PMU to the same devfn. Also, the current code just throws the warning, but still registers the device. The WARN_ON_ONCE() should be removed. The func_id is used by the later event_init() to check if a event->pmu has valid devices. For cpu and mmio uncore PMUs, they are always valid. For pci uncore PMUs, it's set when the PMU is registered. It can be replaced by the pmu->registered. Clean up the func_id. Intel-SIG: commit 3f710be02ea6 perf/x86/intel/uncore: Clean up func_id. PMU GNR support Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Tested-by: Eric Hu <[email protected]> Link: https://lkml.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6d642735cdb6cdb814d2b6c81652caa53ce04842 upstream. The same CXL PMONs support is also avaiable on GNR. Apply spr_uncore_cxlcm and spr_uncore_cxldp to GNR as well. The other units were broken on early HW samples, so they were ignored in the early enabling patch. The issue has been fixed and verified on the later production HW. Add UPI, B2UPI, B2HOT, PCIEX16 and PCIEX8 for GNR. Intel-SIG: commit 6d642735cdb6 perf/x86/intel/uncore: Support more units on Granite Rapids. GNR PMU backporting Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Tested-by: Eric Hu <[email protected]> Link: https://lkml.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit e415c1493fa1e93afaec697385b8952d932c41bc upstream. Add events v1.00. Bring in the events from: https://github.com/intel/perfmon/tree/main/CWF/events Co-developed-by: Caleb Biggers <[email protected]> Intel-SIG: commit e415c1493fa1 perf vendor events: Add Clearwaterforest events. ClearWater Forrest PMU backporting Signed-off-by: Caleb Biggers <[email protected]> Acked-by: Kan Liang <[email protected]> Signed-off-by: Ian Rogers <[email protected]> Tested-by: Thomas Falcon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Namhyung Kim <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 9828a1c upstream. New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* uncore patches into one. ] Intel-SIG: commit 9828a1c perf/x86/intel/uncore: Switch to new Intel CPU model defines. ClearWater Forrest PMU backporting Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181501.41557-1-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit the upstream. same as the previous Sierra Forest. The only difference is the event list, which will be supported in the perf tool later. Intel-SIG: commit the perf/x86/intel/uncore: Add Clearwater Forest support. ClearWater Forrest PMU backporting Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lkml.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit cf002dafedd06241175e4dbce39ba90a4b75822c upstream. Starting from the Panther Lake, the discovery table mechanism is also supported in client platforms. The difference is that the portal of the global discovery table is retrieved from an MSR. The layout of discovery tables are the same as the server platforms. Factor out __parse_discovery_table() to parse discover tables. The uncore PMON is Die scope. Need to parse the discovery tables for each die. Intel-SIG: commit cf002dafedd0 perf/x86/intel/uncore: Support MSR portal for discovery tables. ClearWater Forrest PMU backporting Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Reviewed-by: Dapeng Mi <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit fca24bf2b6b619770d7f1222c0284791d7766239 upstream. For a server platform, the MMIO map size is always 0x4000. However, a client platform may have a smaller map size. Make the map size customizable. Intel-SIG: commit fca24bf2b6b6 perf/x86/intel/uncore: Support customized MMIO map size. ClearWater Forrest PMU backporting Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Reviewed-by: Dapeng Mi <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
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depends on PR#72
support Intel new platform Clearwater Forrest PMU for uncore and event
6d642735cdb6,perf/x86/intel/uncore: Support more units on Granite Rapids,2025-01-10 18:16:50,Kan Liang [email protected],v6.14-rc1
3f710be02ea6,perf/x86/intel/uncore: Clean up func_id,2025-01-10 18:16:50,Kan Liang [email protected],v6.14-rc1
e415c1493fa1,perf vendor events: Add Clearwaterforest events,2025-02-12 19:54:38,Ian Rogers [email protected],v6.15-rc1,v6.15-rc1
fca24bf2b6b6,perf/x86/intel/uncore: Support customized MMIO map size,2025-07-09 13:40:19,Kan Liang [email protected],v6.17-rc1,v6.17-rc1
cf002dafedd0,perf/x86/intel/uncore: Support MSR portal for discovery tables,2025-07-09 13:40:19,Kan Liang [email protected],v6.17-rc1,v6.17-rc1
b6ccddd6fe1f,perf/x86/intel/uncore: Add Clearwater Forest support,2024-12-17 17:47:23,Kan Liang [email protected],v6.13-rc5,v6.13-rc5
support IFM for uncore
9828a1c,perf/x86/intel/uncore: Switch to new Intel CPU model defines,2024-04-29 10:30:39,Tony Luck [email protected],v6.10-rc1
Testing Result: PASS
Event test: PASS
perf stat -e LONGEST_LAT_CACHE.MISS,LONGEST_LAT_CACHE.REFERENCE -a sleep 1
Performance counter stats for 'system wide':
perf record -e instructions -Iax,bx -b -c 100000 sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.027 MB perf.data (13 samples) ]
[root@CS17CA101IS1501 ~]# perf record -e branches -Iax,bx -b -c 10000 sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.041 MB perf.data (29 samples) ]
uncore test: PASS
ls -d /sys/devices/uncore* |grep uncore
/sys/devices/uncore_b2cmi_0
/sys/devices/uncore_b2cmi_1
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/sys/devices/uncore_mdf_sbo_79
/sys/devices/uncore_mdf_sbo_8
/sys/devices/uncore_mdf_sbo_9
/sys/devices/uncore_pciex16_1
/sys/devices/uncore_pciex16_2
/sys/devices/uncore_pciex16_3
/sys/devices/uncore_pciex16_8
/sys/devices/uncore_pciex8
/sys/devices/uncore_pcu_0
/sys/devices/uncore_pcu_1
/sys/devices/uncore_pcu_2
/sys/devices/uncore_pcu_3
/sys/devices/uncore_pcu_4
/sys/devices/uncore_ubox
/sys/devices/uncore_upi_0
/sys/devices/uncore_upi_1
/sys/devices/uncore_upi_2
/sys/devices/uncore_upi_3
/sys/devices/uncore_upi_4
/sys/devices/uncore_upi_5