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Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF.

Note: this PR also includes all the patches in #60, because it depends on the CWF CPUID support in that PR.

Tests:
The OOB CPU frequency control is only available on certain SKUs. Tested this patch series on regular SKUs and no regression found.

aegl and others added 7 commits August 27, 2025 22:33
commit 090e3be upstream.

Server product based on the Atom Darkmont core.

Intel-SIG: commit 090e3be x86/cpu: Add model number for Intel Clearwater Forest processor.
BACKPORTING NEW CPU IFM

Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <[email protected]>
commit 8a8a9c9 upstream.

This one is the regular laptop CPU.

Intel-SIG: commit 8a8a9c9 x86/cpu: Add model number for another Intel Arrow Lake mobile processor.
BACKPORTING NEW CPU IFM

Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <[email protected]>
commit a9d0adc upstream.

Refactor struct cpuinfo_x86 so that the vendor, family, and model
fields are overlaid in a union with a 32-bit field that combines
all three (together with a one byte reserved field in the upper
byte).

This will make it easy, cheap, and reliable to check all three
values at once.

See

  https://lore.kernel.org/r/Zgr6kT8oULbnmEXx@agluck-desk3

for why the ordering is (low-to-high bits):

  (vendor, family, model)

  [ bp: Move comments over the line, add the backstory about the
    particular order of the fields. ]

Intel-SIG: commit a9d0adc x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86.
BACKPORTING NEW CPU IFM

Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <[email protected]>
commit f055b62 upstream.

New CPU #defines encode vendor and family as well as model.

Update the example usage comment in arch/x86/kernel/cpu/match.c

Intel-SIG: commit f055b62 x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h.
BACKPORTING NEW CPU IFM

Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <[email protected]>
commit 7e1c3f5 upstream.

Prevent intel_pstate from loading when OOB (Out Of Band) P-states mode is
enabled in Emerald Rapids.

The OOB identifying bits are same as for the prior generation CPUs
like Sapphire Rapids servers, so also add Emerald Rapids to the
intel_pstate_cpu_oob_ids[] list.

Intel-SIG: commit 7e1c3f5 cpufreq: intel_pstate: Support Emerald Rapids OOB mode
Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF

Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
[ Zhang Rui: resolve conflict (X86_MATCH changed) and amend commit log ]
Signed-off-by: Zhang Rui <[email protected]>
commit 3ca2a3d upstream.

Prevent intel_pstate from loading when OOB (Out Of Band) P-states mode is
enabled.

The OOB identifying bits are same as for the prior generation CPUs like
Emerald Rapids servers. Add Granite Rapids and Sierra Forest CPU models to
intel_pstate_cpu_oob_ids[].

Intel-SIG: commit 3ca2a3d cpufreq: intel_pstate: Support Granite Rapids and Sierra Forest OOB mode
Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF

Signed-off-by: Srinivas Pandruvada <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Rafael J. Wysocki <[email protected]>
[ Zhang Rui: resolve conflict (X86_MATCH changed) and amend commit log ]
Signed-off-by: Zhang Rui <[email protected]>
commit 3ead77989c20cb2d774a3b6045d7a928b6fb53ed upstream.

Prevent intel_pstate from loading when OOB (Out Of Band) P-states mode is
enabled.

Intel-SIG: commit 3ead77989c20 cpufreq: intel_pstate: Support Clearwater Forest OOB mode
Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF

Signed-off-by: Srinivas Pandruvada <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Rafael J. Wysocki <[email protected]>
[ Zhang Rui: resolve conflict (X86_MATCH changed) and amend commit log ]
Signed-off-by: Zhang Rui <[email protected]>
x56Jason added a commit to openvelinux/kernel-intel that referenced this pull request Nov 10, 2025
…te-OOB-EMR-GNR-SRF-CWF' into intel-6.6-velinux

Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF.

Note: this PR also includes all the patches in openvelinux#60, because it depends on the CWF CPUID support in that PR.

Tests:
The OOB CPU frequency control is only available on certain SKUs. Tested this patch series on regular SKUs and no regression found.
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3 participants