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[MachineScheduler] Add option to control reordering for store/load clustering #75338

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Merged
merged 2 commits into from
Jan 16, 2024
Merged

[MachineScheduler] Add option to control reordering for store/load clustering #75338

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037f49e
[MachineScheduler] Add option to control reordering for store/load cl…
asb Dec 13, 2023
7e11d11
Add comment for ReorderWhileClustering argument
asb Jan 4, 2024
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10 changes: 8 additions & 2 deletions llvm/include/llvm/CodeGen/MachineScheduler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1347,13 +1347,19 @@ ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);
/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);

/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
std::unique_ptr<ScheduleDAGMutation>
createLoadClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
const TargetRegisterInfo *TRI,
bool ReorderWhileClustering = false);

/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
std::unique_ptr<ScheduleDAGMutation>
createStoreClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
const TargetRegisterInfo *TRI,
bool ReorderWhileClustering = false);

std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
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31 changes: 20 additions & 11 deletions llvm/lib/CodeGen/MachineScheduler.cpp
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Expand Up @@ -1743,11 +1743,14 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
bool IsLoad;
bool ReorderWhileClustering;

public:
BaseMemOpClusterMutation(const TargetInstrInfo *tii,
const TargetRegisterInfo *tri, bool IsLoad)
: TII(tii), TRI(tri), IsLoad(IsLoad) {}
const TargetRegisterInfo *tri, bool IsLoad,
bool ReorderWhileClustering)
: TII(tii), TRI(tri), IsLoad(IsLoad),
ReorderWhileClustering(ReorderWhileClustering) {}

void apply(ScheduleDAGInstrs *DAGInstrs) override;

Expand All @@ -1763,14 +1766,16 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
class StoreClusterMutation : public BaseMemOpClusterMutation {
public:
StoreClusterMutation(const TargetInstrInfo *tii,
const TargetRegisterInfo *tri)
: BaseMemOpClusterMutation(tii, tri, false) {}
const TargetRegisterInfo *tri,
bool ReorderWhileClustering)
: BaseMemOpClusterMutation(tii, tri, false, ReorderWhileClustering) {}
};

class LoadClusterMutation : public BaseMemOpClusterMutation {
public:
LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
: BaseMemOpClusterMutation(tii, tri, true) {}
LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri,
bool ReorderWhileClustering)
: BaseMemOpClusterMutation(tii, tri, true, ReorderWhileClustering) {}
};

} // end anonymous namespace
Expand All @@ -1779,15 +1784,19 @@ namespace llvm {

std::unique_ptr<ScheduleDAGMutation>
createLoadClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
return EnableMemOpCluster ? std::make_unique<LoadClusterMutation>(TII, TRI)
const TargetRegisterInfo *TRI,
bool ReorderWhileClustering) {
return EnableMemOpCluster ? std::make_unique<LoadClusterMutation>(
TII, TRI, ReorderWhileClustering)
: nullptr;
}

std::unique_ptr<ScheduleDAGMutation>
createStoreClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
return EnableMemOpCluster ? std::make_unique<StoreClusterMutation>(TII, TRI)
const TargetRegisterInfo *TRI,
bool ReorderWhileClustering) {
return EnableMemOpCluster ? std::make_unique<StoreClusterMutation>(
TII, TRI, ReorderWhileClustering)
: nullptr;
}

Expand Down Expand Up @@ -1840,7 +1849,7 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(

SUnit *SUa = MemOpa.SU;
SUnit *SUb = MemOpb.SU;
if (SUa->NodeNum > SUb->NodeNum)
if (!ReorderWhileClustering && SUa->NodeNum > SUb->NodeNum)
std::swap(SUa, SUb);

// FIXME: Is this check really required?
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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Expand Up @@ -348,7 +348,8 @@ class RISCVPassConfig : public TargetPassConfig {
ScheduleDAGMILive *DAG = nullptr;
if (EnableMISchedLoadClustering) {
DAG = createGenericSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(createLoadClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
if (ST.hasMacroFusion()) {
DAG = DAG ? DAG : createGenericSchedLive(C);
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/misched-load-clustering.ll
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Expand Up @@ -23,10 +23,10 @@ define i32 @load_clustering_1(ptr nocapture %p) {
; LDCLUSTER: ********** MI Scheduling **********
; LDCLUSTER-LABEL: load_clustering_1:%bb.0
; LDCLUSTER: *** Final schedule for %bb.0 ***
; LDCLUSTER: SU(5): %6:gpr = LW %0:gpr, 16
; LDCLUSTER: SU(1): %1:gpr = LW %0:gpr, 12
; LDCLUSTER: SU(2): %2:gpr = LW %0:gpr, 8
; LDCLUSTER: SU(4): %4:gpr = LW %0:gpr, 4
; LDCLUSTER: SU(2): %2:gpr = LW %0:gpr, 8
; LDCLUSTER: SU(1): %1:gpr = LW %0:gpr, 12
; LDCLUSTER: SU(5): %6:gpr = LW %0:gpr, 16
entry:
%arrayidx0 = getelementptr inbounds i32, ptr %p, i32 3
%val0 = load i32, i32* %arrayidx0
Expand Down