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| 1 | +//===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// |
| 9 | +// This file implements a target parser to recognise hardware features |
| 10 | +// FOR RISC-V CPUS. |
| 11 | +// |
| 12 | +//===----------------------------------------------------------------------===// |
| 13 | + |
| 14 | +#ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H |
| 15 | +#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H |
| 16 | + |
| 17 | +#include "llvm/ADT/StringRef.h" |
| 18 | +#include <vector> |
| 19 | + |
| 20 | +namespace llvm { |
| 21 | +namespace RISCV { |
| 22 | + |
| 23 | +// We use 64 bits as the known part in the scalable vector types. |
| 24 | +static constexpr unsigned RVVBitsPerBlock = 64; |
| 25 | + |
| 26 | +enum CPUKind : unsigned { |
| 27 | +#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM, |
| 28 | +#define TUNE_PROC(ENUM, NAME) CK_##ENUM, |
| 29 | +#include "llvm/TargetParser/RISCVTargetParserDef.inc" |
| 30 | +}; |
| 31 | + |
| 32 | +enum FeatureKind : unsigned { |
| 33 | + FK_INVALID = 0, |
| 34 | + FK_NONE = 1, |
| 35 | + FK_64BIT = 1 << 2, |
| 36 | +}; |
| 37 | + |
| 38 | +bool checkCPUKind(CPUKind Kind, bool IsRV64); |
| 39 | +bool checkTuneCPUKind(CPUKind Kind, bool IsRV64); |
| 40 | +CPUKind parseCPUKind(StringRef CPU); |
| 41 | +CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64); |
| 42 | +StringRef getMArchFromMcpu(StringRef CPU); |
| 43 | +void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); |
| 44 | +void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); |
| 45 | +bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features); |
| 46 | + |
| 47 | +} // namespace RISCV |
| 48 | +} // namespace llvm |
| 49 | + |
| 50 | +#endif |
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