Revert "[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen."

This reverts commit cf7a830.

Author: fpetrogalli

clang/lib/Basic/Targets/RISCV.cpp

@@ -15,8 +15,8 @@
 #include "clang/Basic/MacroBuilder.h"
 #include "clang/Basic/TargetBuiltins.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 #include <optional>
 
 using namespace clang;

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

@@ -17,8 +17,8 @@
 #include "llvm/Support/Error.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;

llvm/include/llvm/CMakeLists.txt

@@ -1,7 +1,6 @@
 add_subdirectory(IR)
 add_subdirectory(Support)
 add_subdirectory(Frontend)
-add_subdirectory(TargetParser)
 
 # If we're doing an out-of-tree build, copy a module map for generated
 # header files into the build area.

llvm/include/llvm/TargetParser/CMakeLists.txt

@@ -0,0 +1,35 @@
+#ifndef PROC
+#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
+#endif
+
+PROC(INVALID, {"invalid"}, FK_INVALID, {""})
+PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
+PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
+PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
+PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
+PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
+PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
+PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
+PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
+PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
+PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
+PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
+PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
+PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SYNTACORE_SCR1_MAX, {"syntacore-scr1-max"}, FK_NONE, {"rv32imc"})
+
+#undef PROC
+
+#ifndef TUNE_PROC
+#define TUNE_PROC(ENUM, NAME)
+#endif
+
+TUNE_PROC(GENERIC, "generic")
+TUNE_PROC(ROCKET, "rocket")
+TUNE_PROC(SIFIVE_7, "sifive-7-series")
+
+#undef TUNE_PROC

llvm/include/llvm/TargetParser/RISCVTargetParser.def

@@ -154,6 +154,34 @@ void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);
 IsaVersion getIsaVersion(StringRef GPU);
 
 } // namespace AMDGPU
+
+namespace RISCV {
+
+// We use 64 bits as the known part in the scalable vector types.
+static constexpr unsigned RVVBitsPerBlock = 64;
+
+enum CPUKind : unsigned {
+#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
+#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
+#include "RISCVTargetParser.def"
+};
+
+enum FeatureKind : unsigned {
+  FK_INVALID = 0,
+  FK_NONE = 1,
+  FK_64BIT = 1 << 2,
+};
+
+bool checkCPUKind(CPUKind Kind, bool IsRV64);
+bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
+CPUKind parseCPUKind(StringRef CPU);
+CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
+StringRef getMArchFromMcpu(StringRef CPU);
+void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
+void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
+bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
+
+} // namespace RISCV
 } // namespace llvm
 
 #endif

llvm/include/llvm/TargetParser/RISCVTargetParser.h

@@ -3,4 +3,3 @@ module LLVM_Extern_IR_Attributes_Gen {}
 module LLVM_Extern_IR_Intrinsics_Gen {}
 module LLVM_Extern_IR_Intrinsics_Enum {}
 module LLVM_Extern_Utils_DataTypes {}
-module LLVM_Extern_TargetParser_Gen {}

llvm/include/llvm/TargetParser/TargetParser.h

@@ -25,7 +25,3 @@ module LLVM_Extern_Utils_DataTypes {
   header "Support/DataTypes.h"
   export *
 }
-
-module LLVM_Extern_TargetParser_Gen {
-  textual header "TargetParser/RISCVTargetParserDef.inc"
-}

llvm/include/llvm/module.extern.modulemap

@@ -391,16 +391,6 @@ module LLVM_Transforms {
 
 extern module LLVM_Extern_Utils_DataTypes "module.extern.modulemap"
 
-// Build the module with the tablegen-generated files needed by the
-// TargetParser module before building the TargetParser module itself.
-module TargetParserGen {
-  module RISCVTargetParserDef {
-    header "TargetParser/RISCVTargetParser.h"
-    extern module LLVM_Extern_TargetParser_Gen "module.extern.modulemap"
-    export *
-  }
-}
-
 // A module covering ADT/ and Support/. These are intertwined and
 // codependent, and notionally form a single module.
 module LLVM_Utils {
@@ -437,6 +427,7 @@ module LLVM_Utils {
     textual header "TargetParser/AArch64TargetParser.def"
     textual header "TargetParser/ARMTargetParser.def"
     textual header "TargetParser/CSKYTargetParser.def"
+    textual header "TargetParser/RISCVTargetParser.def"
     textual header "TargetParser/X86TargetParser.def"
     textual header "TargetParser/LoongArchTargetParser.def"
   }