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[CIR] Add syncscope to AtomicCmpXchgOp #1419

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Merged
merged 4 commits into from
Mar 1, 2025
Merged

[CIR] Add syncscope to AtomicCmpXchgOp #1419

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877cc45
[CIR] Add syncscope to AtomicCmpXchgOp
FantasqueX Feb 27, 2025
ea6cb30
format code
FantasqueX Feb 27, 2025
1213028
format code
FantasqueX Feb 28, 2025
216e102
add singlethread test
FantasqueX Feb 28, 2025
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26 changes: 14 additions & 12 deletions clang/include/clang/CIR/Dialect/IR/CIROps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5515,6 +5515,18 @@ def AtomicXchg : CIR_Op<"atomic.xchg", [AllTypesMatch<["result", "val"]>]> {
let hasVerifier = 0;
}

def MemScope_SingleThread : I32EnumAttrCase<"MemScope_SingleThread",
0, "single_thread">;
def MemScope_System : I32EnumAttrCase<"MemScope_System",
1, "system">;

def MemScopeKind : I32EnumAttr<
"MemScopeKind",
"Memory Scope Enumeration",
[MemScope_SingleThread, MemScope_System]> {
let cppNamespace = "::cir";
}

def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
[AllTypesMatch<["old", "expected", "desired"]>]> {
let summary = "Atomic compare exchange";
Expand All @@ -5537,6 +5549,7 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
CIR_AnyType:$desired,
Arg<MemOrder, "success memory order">:$succ_order,
Arg<MemOrder, "failure memory order">:$fail_order,
OptionalAttr<MemScopeKind>:$syncscope,
OptionalAttr<I64Attr>:$alignment,
UnitAttr:$weak,
UnitAttr:$is_volatile);
Expand All @@ -5549,6 +5562,7 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
`success` `=` $succ_order `,`
`failure` `=` $fail_order
`)`
(`syncscope` `(` $syncscope^ `)`)?
(`align` `(` $alignment^ `)`)?
(`weak` $weak^)?
(`volatile` $is_volatile^)?
Expand All @@ -5558,18 +5572,6 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
let hasVerifier = 0;
}

def MemScope_SingleThread : I32EnumAttrCase<"MemScope_SingleThread",
0, "single_thread">;
def MemScope_System : I32EnumAttrCase<"MemScope_System",
1, "system">;

def MemScopeKind : I32EnumAttr<
"MemScopeKind",
"Memory Scope Enumeration",
[MemScope_SingleThread, MemScope_System]> {
let cppNamespace = "::cir";
}

def AtomicFence : CIR_Op<"atomic.fence"> {
let summary = "Atomic thread fence";
let description = [{
Expand Down
10 changes: 6 additions & 4 deletions clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -415,7 +415,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
Address Val2, uint64_t Size,
cir::MemOrder SuccessOrder,
cir::MemOrder FailureOrder,
llvm::SyncScope::ID Scope) {
cir::MemScopeKind Scope) {
auto &builder = CGF.getBuilder();
auto loc = CGF.getLoc(E->getSourceRange());
auto Expected = builder.createLoad(loc, Val1);
Expand All @@ -425,6 +425,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
loc, Expected.getType(), boolTy, Ptr.getPointer(), Expected, Desired,
cir::MemOrderAttr::get(&CGF.getMLIRContext(), SuccessOrder),
cir::MemOrderAttr::get(&CGF.getMLIRContext(), FailureOrder),
cir::MemScopeKindAttr::get(&CGF.getMLIRContext(), Scope),
builder.getI64IntegerAttr(Ptr.getAlignment().getAsAlign().value()));
cmpxchg.setIsVolatile(E->isVolatile());
cmpxchg.setWeak(IsWeak);
Expand Down Expand Up @@ -452,7 +453,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
static void emitAtomicCmpXchgFailureSet(
CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak, Address Dest, Address Ptr,
Address Val1, Address Val2, mlir::Value FailureOrderVal, uint64_t Size,
cir::MemOrder SuccessOrder, llvm::SyncScope::ID Scope) {
cir::MemOrder SuccessOrder, cir::MemScopeKind Scope) {

cir::MemOrder FailureOrder;
if (auto ordAttr = getConstOpIntAttr(FailureOrderVal)) {
Expand Down Expand Up @@ -541,7 +542,8 @@ static void emitAtomicCmpXchgFailureSet(
static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
Address Ptr, Address Val1, Address Val2,
mlir::Value IsWeak, mlir::Value FailureOrder,
uint64_t Size, cir::MemOrder Order, uint8_t Scope) {
uint64_t Size, cir::MemOrder Order,
cir::MemScopeKind Scope) {
assert(!cir::MissingFeatures::syncScopeID());
StringRef Op;

Expand Down Expand Up @@ -797,7 +799,7 @@ static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *Expr, Address Dest,
if (!ScopeModel) {
assert(!cir::MissingFeatures::syncScopeID());
emitAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
Order, /*FIXME(cir): LLVM default scope*/ 1);
Order, cir::MemScopeKind::MemScope_System);
return;
}

Expand Down
8 changes: 5 additions & 3 deletions clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ static RValue emitBinaryAtomicPost(CIRGenFunction &cgf,
return RValue::get(result);
}

static mlir::Value MakeAtomicCmpXchgValue(CIRGenFunction &cgf,
static mlir::Value makeAtomicCmpXchgValue(CIRGenFunction &cgf,
const CallExpr *expr,
bool returnBool) {
QualType typ = returnBool ? expr->getArg(1)->getType() : expr->getType();
Expand All @@ -341,6 +341,8 @@ static mlir::Value MakeAtomicCmpXchgValue(CIRGenFunction &cgf,
cir::MemOrder::SequentiallyConsistent),
MemOrderAttr::get(&cgf.getMLIRContext(),
cir::MemOrder::SequentiallyConsistent),
MemScopeKindAttr::get(&cgf.getMLIRContext(),
cir::MemScopeKind::MemScope_System),
builder.getI64IntegerAttr(destAddr.getAlignment().getAsAlign().value()));

return returnBool ? op.getResult(1) : op.getResult(0);
Expand Down Expand Up @@ -1854,14 +1856,14 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
case Builtin::BI__sync_val_compare_and_swap_4:
case Builtin::BI__sync_val_compare_and_swap_8:
case Builtin::BI__sync_val_compare_and_swap_16:
return RValue::get(MakeAtomicCmpXchgValue(*this, E, false));
return RValue::get(makeAtomicCmpXchgValue(*this, E, false));

case Builtin::BI__sync_bool_compare_and_swap_1:
case Builtin::BI__sync_bool_compare_and_swap_2:
case Builtin::BI__sync_bool_compare_and_swap_4:
case Builtin::BI__sync_bool_compare_and_swap_8:
case Builtin::BI__sync_bool_compare_and_swap_16:
return RValue::get(MakeAtomicCmpXchgValue(*this, E, true));
return RValue::get(makeAtomicCmpXchgValue(*this, E, true));

case Builtin::BI__sync_swap_1:
case Builtin::BI__sync_swap_2:
Expand Down
3 changes: 2 additions & 1 deletion clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
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Expand Up @@ -3210,11 +3210,12 @@ mlir::LogicalResult CIRToLLVMAtomicCmpXchgLowering::matchAndRewrite(
auto expected = adaptor.getExpected();
auto desired = adaptor.getDesired();

// FIXME: add syncscope.
auto cmpxchg = rewriter.create<mlir::LLVM::AtomicCmpXchgOp>(
op.getLoc(), adaptor.getPtr(), expected, desired,
getLLVMAtomicOrder(adaptor.getSuccOrder()),
getLLVMAtomicOrder(adaptor.getFailOrder()));
if (const auto ss = adaptor.getSyncscope(); ss.has_value())
cmpxchg.setSyncscope(getLLVMSyncScope(ss.value()));
cmpxchg.setAlignment(adaptor.getAlignment());
cmpxchg.setWeak(adaptor.getWeak());
cmpxchg.setVolatile_(adaptor.getIsVolatile());
Expand Down
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