arcv: Fix missing vsetvli generation for arcv_vmv instructions. #175
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MichielDerhaeg
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And the other tests? |
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I've also updated the |
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There is also vmv(i)_s_v |
Both tests have been updated. Also rebased on top of the new changes on |
The arcv_vmv RTL patterns were not generating vsetvli instructions because they lacked the proper RVV predication structure. This caused the vector configuration to not be set up before executing the arcv.vmv.v.s and arcv.vmv.s.v instructions. This patch restructures the arcv_vmv patterns to follow the standard RVV predicated instruction format by: - Wrapping the instruction in an if_then_else with UNSPEC_VPREDICATE. - Adding VL_REGNUM and VTYPE_REGNUM registers to the predication. - Moving the actual instruction logic to an inner unspec. This structure matches other ARCV vector instructions (like vnorm) and enables the vsetvl pass to properly insert vsetvli instructions before the arcv_vmv operations. Signed-off-by: Luis Silva <[email protected]>
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MichielDerhaeg
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The arcv_vmv RTL patterns were not generating vsetvli instructions because they lacked the proper RVV predication structure. This caused the vector configuration to not be set up before executing the arcv.vmv.v.s and arcv.vmv.s.v instructions.
This patch restructures the arcv_vmv patterns to follow the standard RVV predicated instruction format by:
This structure matches other ARCV vector instructions (like vnorm) and enables the vsetvl pass to properly insert vsetvli instructions before the arcv_vmv operations.