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JIT ARM64-SVE: Remove INS_SCALABLE_OPTS_SHIFT #99258

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Merged
merged 9 commits into from
Mar 7, 2024
Merged

JIT ARM64-SVE: Remove INS_SCALABLE_OPTS_SHIFT #99258

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f15d19e
Remove INS_SCALABLE_OPTS_SHIFT
amanasifkhalid Mar 4, 2024
a9c9815
Merge from main
amanasifkhalid Mar 5, 2024
ce4dc70
Convert imm in emitIns
amanasifkhalid Mar 5, 2024
4bb3e35
Remove sopt arg from emitIns_R_I
amanasifkhalid Mar 5, 2024
02ddf43
Style
amanasifkhalid Mar 5, 2024
131ec68
Merge branch 'main' into scalable-shift
jkotas Mar 5, 2024
d248988
Fix code dup
amanasifkhalid Mar 6, 2024
fd039c0
Revert
amanasifkhalid Mar 6, 2024
462447c
Fix
amanasifkhalid Mar 6, 2024
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3 changes: 1 addition & 2 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2241,8 +2241,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size,
{
if (emitter::emitIns_valid_imm_for_mov(imm, size))
{
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE,
INS_SCALABLE_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
}
else
{
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40 changes: 20 additions & 20 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6666,20 +6666,20 @@ void CodeGen::genArm64EmitterUnitTestsSve()
// IF_SVE_EB_1A
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V0, -128,
INS_OPTS_SCALABLE_B); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V1, 0,
INS_OPTS_SCALABLE_H); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V2, 5,
INS_OPTS_SCALABLE_S); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V3, 127,
INS_OPTS_SCALABLE_D); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V4, 0,
INS_OPTS_SCALABLE_B); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V5, -128, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V6, 5, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V7, 127, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V4, 256,
INS_OPTS_SCALABLE_D); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V5, -32768,
INS_OPTS_SCALABLE_H); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V6, 1280,
INS_OPTS_SCALABLE_S); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V7, 32512,
INS_OPTS_SCALABLE_D); // MOV <Zd>.<T>, #<imm>{, <shift>}

// IF_SVE_EB_1B
theEmitter->emitIns_R(INS_sve_fmov, EA_SCALABLE, REG_V0, INS_OPTS_SCALABLE_B); // FMOV <Zd>.<T>, #0.0
Expand All @@ -6690,18 +6690,18 @@ void CodeGen::genArm64EmitterUnitTestsSve()
// IF_SVE_EC_1A
theEmitter->emitIns_R_I(INS_sve_add, EA_SCALABLE, REG_V0, 0,
INS_OPTS_SCALABLE_B); // ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_SCALABLE, REG_V2, 1,
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_SCALABLE, REG_V1, 5,
INS_OPTS_SCALABLE_H); // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_SCALABLE, REG_V2, 128,
INS_OPTS_SCALABLE_S); // SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sub, EA_SCALABLE, REG_V3, 128,
theEmitter->emitIns_R_I(INS_sve_sub, EA_SCALABLE, REG_V3, 255,
INS_OPTS_SCALABLE_D); // SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_subr, EA_SCALABLE, REG_V4, 255,
INS_OPTS_SCALABLE_B); // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_SCALABLE, REG_V5, 5, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_SCALABLE, REG_V6, 255, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_SHIFT); // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_subr, EA_SCALABLE, REG_V4, 256,
INS_OPTS_SCALABLE_D); // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_SCALABLE, REG_V5, 1280,
INS_OPTS_SCALABLE_H); // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_SCALABLE, REG_V6, 65280,
INS_OPTS_SCALABLE_S); // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}

// IF_SVE_EG_3A
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_SCALABLE, REG_V1, REG_V2, REG_V0, 0,
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21 changes: 11 additions & 10 deletions src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1458,16 +1458,6 @@ class emitter
assert(!idIsSmallDsc());
idAddr()->_idRegBit = val ? 1 : 0;
}
bool idOptionalShift() const
{
assert(!idIsSmallDsc());
return (idAddr()->_idRegBit == 1);
}
void idOptionalShift(bool val)
{
assert(!idIsSmallDsc());
idAddr()->_idRegBit = val ? 1 : 0;
}
insSvePattern idSvePattern() const
{
assert(!idIsSmallDsc());
Expand All @@ -1488,6 +1478,17 @@ class emitter
assert(!idIsSmallDsc());
idAddr()->_idReg4 = (regNumber)idSvePrfop;
}
bool idHasShift() const
{
return !idIsSmallDsc() && (idAddr()->_idRegBit == 1);
}
void idHasShift(bool val)
{
if (!idIsSmallDsc())
{
idAddr()->_idRegBit = val ? 1 : 0;
}
}
#endif // TARGET_ARM64

#endif // TARGET_ARMARCH
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