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Arm64 SVE: Add mask to nonfaulting loads #117606

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Merged
merged 4 commits into from
Jul 15, 2025
Merged

Arm64 SVE: Add mask to nonfaulting loads #117606

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9f47639
Arm64 SVE: Add mask to nonfaulting loads
a74nh Jul 7, 2025
d58d82a
Add apicompat changes
a74nh Jul 14, 2025
0106ca0
Update JITEEVersionIdentifier
a74nh Jul 14, 2025
1aedde3
Fix up EmbeddedLoads test
a74nh Jul 15, 2025
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10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,11 +37,11 @@

#include <minipal/guid.h>

constexpr GUID JITEEVersionIdentifier = { /* 5c7eb9f1-a9cb-4a35-aea6-ae93d1f54c56 */
0x5c7eb9f1,
0xa9cb,
0x4a35,
{0xae, 0xa6, 0xae, 0x93, 0xd1, 0xf5, 0x4c, 0x56}
constexpr GUID JITEEVersionIdentifier = { /* 952f0344-7651-46af-8ef3-a34539af5c4a */
0x952f0344,
0x7651,
0x46af,
{0x8e, 0xf3, 0xa3, 0x45, 0x39, 0xaf, 0x5c, 0x4a}
};

#endif // JIT_EE_VERSIONING_GUID_H
25 changes: 25 additions & 0 deletions src/coreclr/jit/gentree.cpp
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Expand Up @@ -28654,6 +28654,31 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
case NI_Sve_Load2xVectorAndUnzip:
case NI_Sve_Load3xVectorAndUnzip:
case NI_Sve_Load4xVectorAndUnzip:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorNonFaulting:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
addr = Op(2);
break;

Expand Down
44 changes: 6 additions & 38 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -670,38 +670,6 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand..
switch (intrinEmbMask.id)
{
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorNonFaulting:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
{

GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
opt);
break;
}

case NI_Sve_And_Predicates:
case NI_Sve_BitwiseClear_Predicates:
case NI_Sve_Or_Predicates:
Expand Down Expand Up @@ -2175,14 +2143,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
{
if (intrin.numOperands == 2)
if (intrin.numOperands == 3)
{
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR
// register.
assert(op2Reg != REG_NA);
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op2Reg, opt);
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR register.
assert(op3Reg != REG_NA);
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op3Reg, opt);
}
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg);

GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, 0, opt);
break;
}

Expand Down
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