Skip to content

[RISC-V] Add pseudoinstructions to disassembler #102260

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 25 commits into from
May 29, 2024
Merged

[RISC-V] Add pseudoinstructions to disassembler #102260

Show file tree
Hide file tree
Changes from 6 commits
Commits
Show all changes
25 commits
Select commit Hold shift + click to select a range
f501f68
[RISC-V] Reworked emitDispInsName a bit to ease further development
Bajtazar May 15, 2024
344771c
[RISC-V] Little improvements
Bajtazar May 15, 2024
bac35dd
[RISC-V] Refactored code
Bajtazar May 15, 2024
ca5bf3d
[RISC-V] Added mv and nop pseudoinstructions to disasm
Bajtazar May 15, 2024
15d5830
[RISC-V] Added branch pseudos to disasm
Bajtazar May 15, 2024
f27b4f6
[RISC-V] Removed dead code
Bajtazar May 15, 2024
fb27640
[RISC-V] Fixes
Bajtazar May 15, 2024
0cf743e
[RISC-V] Added j pseudoinstruction to disasm
Bajtazar May 15, 2024
a9964cb
[RISC-V] Improved readability
Bajtazar May 15, 2024
a011c43
[RISC-V] Fixed mov pseudoinstruction
Bajtazar May 15, 2024
ebf66d9
Revert "[RISC-V] Fixed mov pseudoinstruction"
Bajtazar May 15, 2024
258b0c6
[RISC-V] Fixed mov printing name
Bajtazar May 16, 2024
dcba8e1
[RISC-V] After review changes
Bajtazar May 16, 2024
f100010
[RISC-V] More fixes after review
Bajtazar May 16, 2024
d69fa7b
[RISC-V] Adjusted 32-bit shift disasm to changes
Bajtazar May 16, 2024
92c0cd2
[RISC-V] Fixed bug
Bajtazar May 16, 2024
b7e4f65
[RISC-V] Fixed comment
Bajtazar May 16, 2024
093193b
[RISC-V] Changed constants' literal type
Bajtazar May 16, 2024
cda08a2
[RISC-V] Added more constants
Bajtazar May 16, 2024
e9b73ef
[RISC-V] Reinforced printing 1
Bajtazar May 16, 2024
5fe1e11
[RISC-V] Reinforced printing 2
Bajtazar May 16, 2024
71644f3
[RISC-V] Fixed bug
Bajtazar May 16, 2024
a3c4f19
[RISC-V] Resolved more bugs
Bajtazar May 16, 2024
6869460
[RISC-V] Removed dead assert
Bajtazar May 22, 2024
a4381bd
Merge branch 'main' into riscv-add-pseudo-to-disasm
Bajtazar May 28, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
79 changes: 57 additions & 22 deletions src/coreclr/jit/emitriscv64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3357,6 +3357,7 @@ static const char* const RegNames[] =

bool emitter::emitDispBranchInstrType(unsigned opcode2, bool is_zero_reg, bool& print_second_reg) const
{
print_second_reg = true;
switch (opcode2)
{
case 0:
Expand All @@ -3369,19 +3370,15 @@ bool emitter::emitDispBranchInstrType(unsigned opcode2, bool is_zero_reg, bool&
break;
case 4:
printf("blt ");
print_second_reg = true;
break;
case 5:
printf("bge ");
print_second_reg = true;
break;
case 6:
printf("bltu");
print_second_reg = true;
break;
case 7:
printf("bgeu");
print_second_reg = true;
break;
default:
return false;
Expand Down Expand Up @@ -3524,25 +3521,33 @@ void emitter::emitDispInsName(
switch (opcode2)
{
case 0x0: // ADDI & MV & NOP
if (imm12 != 0)
if (code == emitInsCode(INS_nop))
{
printLength = printf("addi");
printf("nop\n");
return;
}
else if ((rd != REG_ZERO) || (rs1 != REG_ZERO))
else if (imm12 != 0)
{
printLength = printf("mv");
hasImmediate = false;
printLength = printf("addi");
}
else
{
printf("nop\n");
return;
printLength = printf("mv");
hasImmediate = false;
}
break;
case 0x1: // SLLI
{
unsigned funct6 = (imm12 >> 6) & 0x3f;
// SLLI's instruction code's upper 6 bits have to be equal to zero
if (funct6)
{
return emitDispIllegalInstruction(code);
}
printLength = printf("slli");
imm12 &= 0x3f; // 6 BITS for SHAMT in RISCV64
break;
}
break;
case 0x2: // SLTI
printLength = printf("slti");
break;
Expand All @@ -3554,9 +3559,20 @@ void emitter::emitDispInsName(
isHex = true;
break;
case 0x5: // SRLI & SRAI
printLength = printf((((code >> 30) & 0x1) == 0) ? "srli" : "srai");
{
static constexpr unsigned kLogicalShiftFunct6 = 0x00;
static constexpr unsigned kArithmeticShiftFunct6 = 0x10;

unsigned funct6 = (imm12 >> 6) & 0x3f;
bool isLogicalShift = funct6 == kLogicalShiftFunct6;
if ((!isLogicalShift) && (funct6 != kArithmeticShiftFunct6))
{
return emitDispIllegalInstruction(code);
}
printLength = printf(isLogicalShift ? "srli" : "srai");
imm12 &= 0x3f; // 6BITS for SHAMT in RISCV64
break;
}
break;
case 0x6: // ORI
printLength = printf("ori");
imm12 &= 0xfff;
Expand All @@ -3568,8 +3584,7 @@ void emitter::emitDispInsName(
isHex = true;
break;
default:
printf("RISCV64 illegal instruction: 0x%08X\n", code);
return;
return emitDispIllegalInstruction(code);
}
assert(printLength > 0);
int paddingLength = kMaxInstructionLength - printLength;
Expand Down Expand Up @@ -3599,22 +3614,42 @@ void emitter::emitDispInsName(
case 0x0: // ADDIW
printf("addiw %s, %s, %d\n", rd, rs1, imm12);
return;
case 0x1: // SLLIW
printf("slliw %s, %s, %d\n", rd, rs1, imm12 & 0x3f); // 6 BITS for SHAMT in RISCV64
case 0x1: // SLLIW
{
unsigned funct7 = (imm12 >> 5) & 0x7f;
// SLLIW's instruction code's upper 7 bits have to be equal to zero
if (funct7 == 0)
{
printf("slliw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5 BITS for SHAMT in RISCV64
}
else
{
emitDispIllegalInstruction(code);
}
}
return;
case 0x5: // SRLIW & SRAIW
if (((code >> 30) & 0x1) == 0)
{
static constexpr unsigned kLogicalShiftFunct7 = 0x00;
static constexpr unsigned kArithmeticShiftFunct7 = 0x20;

unsigned funct7 = (imm12 >> 5) & 0x7f;
if (funct7 == kLogicalShiftFunct7)
{
printf("srliw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64
}
else
else if (funct7 == kArithmeticShiftFunct7)
{
printf("sraiw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64
}
else
{
emitDispIllegalInstruction(code);
}
}
return;
default:
printf("RISCV64 illegal instruction: 0x%08X\n", code);
return;
return emitDispIllegalInstruction(code);
}
}
case 0x33:
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/instrsriscv64.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ INST(invalid, "INVALID", 0, BAD_CODE)
INST(nop, "nop", 0, 0x00000013)

//// R_R
INST(mov, "mov", 0, 0x00000013)
INST(mov, "mv", 0, 0x00000013)

////R_I
INST(lui, "lui", 0, 0x00000037)
Expand Down