[Intel-SIG] [Meteor Lake] Sync 6.6 EDAC driver patches to Deepin 6.6

arch/x86/include/asm/mce.h

@@ -78,6 +78,7 @@
 #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
 #define MCACOD_DATA	0x0134	/* Data Load */
 #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
+#define MCACOD_IOERR	0x0e0b	/* Generic I/O error */
 
 /* MCi_MISC register defines */
 #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
@@ -91,6 +92,11 @@
 /* MCi_ADDR register defines */
 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
 
+#define MCI_MISC_PCISEG_MASK	GENMASK_ULL(39, 32)
+#define MCI_MISC_PCISEG(m)	(((m) & MCI_MISC_PCISEG_MASK) >> 32)
+#define MCI_MISC_PCIRID_MASK	GENMASK_ULL(31, 16)
+#define MCI_MISC_PCIRID(m)	(((m) & MCI_MISC_PCIRID_MASK) >> 16)
+
 /* CTL2 register defines */
 #define MCI_CTL2_CMCI_EN		BIT_ULL(30)
 #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL

drivers/edac/Kconfig

@@ -281,6 +281,16 @@ config EDAC_IGEN6
 	  This In-Band ECC is first used on the Elkhart Lake SoC but
 	  may appear on others in the future.
 
+config EDAC_IEH
+	tristate "Intel Integrated Error Handler"
+	depends on PCI && X86_64
+	help
+	  Support for error detection and correction on the Intel
+	  CPU using I/O IEH (Integrated Error Handler). IEHs are PCIe
+	  devices which aggregate and report error events of different
+	  severities from various I/O devices, e.g., PCIe devices and
+	  legacy PCI devices.
+
 config EDAC_MPC85XX
 	bool "Freescale MPC83xx / MPC85xx"
 	depends on FSL_SOC && EDAC=y

drivers/edac/Makefile

@@ -33,6 +33,7 @@ obj-$(CONFIG_EDAC_I7CORE)		+= i7core_edac.o
 obj-$(CONFIG_EDAC_SBRIDGE)		+= sb_edac.o
 obj-$(CONFIG_EDAC_PND2)			+= pnd2_edac.o
 obj-$(CONFIG_EDAC_IGEN6)			+= igen6_edac.o
+obj-$(CONFIG_EDAC_IEH)			+= ieh_edac.o
 obj-$(CONFIG_EDAC_E7XXX)		+= e7xxx_edac.o
 obj-$(CONFIG_EDAC_E752X)		+= e752x_edac.o
 obj-$(CONFIG_EDAC_I82443BXGX)		+= i82443bxgx_edac.o