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[choice] Adds a means to declare a choice group without use #4554
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| Original file line number | Diff line number | Diff line change |
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@@ -3,8 +3,13 @@ | |
| package chisel3 | ||
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| import chisel3.experimental.{BaseModule, SourceInfo} | ||
| import chisel3.internal.Builder | ||
| import chisel3.util.simpleClassName | ||
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| import scala.collection.mutable | ||
| import scala.reflect.runtime.universe._ | ||
| import scala.reflect.runtime.{currentMirror => cm} | ||
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| /** This package contains Chisel language definitions for describing configuration options and their accepted values. | ||
| */ | ||
| package object choice { | ||
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@@ -13,7 +18,7 @@ package object choice { | |
| * | ||
| * @example | ||
| * {{{ | ||
| * import chisel3.option.{Group, Case} | ||
| * import chisel3.choice.{Group, Case} | ||
| * object Platform extends Group { | ||
| * object FPGA extends Case | ||
| * object ASIC extends Case | ||
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@@ -47,4 +52,27 @@ package object choice { | |
| */ | ||
| def ->[T](module: => T): (Case, () => T) = (this, () => module) | ||
| } | ||
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| /** Registers all options in a group with the Builder. | ||
| * This lets Chisel know that this layer should be emitted into FIRRTL text. | ||
| * | ||
| * This API can be used to guarantee that a design will always have certain | ||
| * group defined. This is analagous in spirit to [[layer.addLayer]]. | ||
| */ | ||
| def addGroup[T <: Group: TypeTag](group: T): Unit = { | ||
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| val tpe = typeOf[T] | ||
| val classSymbol = tpe.typeSymbol.asClass | ||
| val classMirror = cm.reflectClass(classSymbol) | ||
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| tpe.members.collect { | ||
| // Look only for inner objects. Note, this is not recursive. | ||
| case m: ModuleSymbol if m.isStatic => | ||
| val instance = cm.reflectModule(m.asModule).instance | ||
| // Confirms the instance is a subtype of Case | ||
| if (cm.classSymbol(instance.getClass).toType <:< typeOf[Case]) { | ||
| Builder.options += instance.asInstanceOf[Case] | ||
| } | ||
| } | ||
| } | ||
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| } | ||
| Original file line number | Diff line number | Diff line change |
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@@ -3,7 +3,7 @@ | |
| package chiselTests | ||
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| import chisel3._ | ||
| import chisel3.choice.{Case, Group, ModuleChoice} | ||
| import chisel3.choice.{addGroup, Case, Group, ModuleChoice} | ||
| import chiselTests.{ChiselFlatSpec, MatchesAndOmits, Utils} | ||
| import _root_.circt.stage.ChiselStage | ||
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@@ -129,3 +129,22 @@ class ModuleChoiceSpec extends ChiselFlatSpec with Utils with MatchesAndOmits { | |
| } | ||
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| } | ||
| class AddGroupSpec extends ChiselFlatSpec with Utils with MatchesAndOmits { | ||
| it should "emit options for a registered group even if there are no consumers" in { | ||
| class ModuleWithoutChoice extends Module { | ||
| addGroup(Platform) | ||
| val out = IO(UInt(8.W)) | ||
| val in = IO(UInt(8.W)) | ||
| out := in | ||
| } | ||
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| val chirrtl = ChiselStage.emitCHIRRTL(new ModuleWithoutChoice, Array("--full-stacktrace")) | ||
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| info("CHIRRTL emission looks correct") | ||
| matchesAndOmits(chirrtl)( | ||
| "option Platform :", | ||
| "FPGA", | ||
| "ASIC" | ||
| )() | ||
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| } | ||
| } | ||
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scala.reflect._doesn't cross-compile with Scala 3, it needs to be put incore/src/main/scala-2/chisel3/