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@ccli8 ccli8 commented Jun 14, 2024

This is a draft of supporting 64-bit clock module index on NuMaker SoC series. Relevant points include:

  1. No m55m1x yet, take m2l31x as an example
  2. Create new binding file nuvoton,numaker-pcc-modidx64.yaml for SoC with 64-bit clock module index
  3. In clock header file for DT, 64-bit value of FOO_MODULE macro expands to two 32-bit cells in BE order
    NOTE: See dt-bindings/clock/numaker_m2l31x_clock.h
    NOTE: Check the link for requirement of 64-bit integer in zephyr
    https://docs.zephyrproject.org/latest/build/dts/intro-syntax-structure.html
  4. In clock ontrol driver,
    1. Type of clock module is fixed to uint64_t
    2. SoC-conditional on type of clock module index on passed to BSP driver
  5. Other drivers (gpio, serial, etc.) also must be soc-conditional on clock module index

This is a draft of supporting 64-bit clock module index on NuMaker SoC series.
Relevant points include:
1. No m55m1x yet, take m2l31x as an example
2. Create new binding file nuvoton,numaker-pcc-modidx64.yaml for SoC with 64-bit clock module index
3. In clock header file for DT, 64-bit value of FOO_MODULE macro expands to two 32-bit cells in BE order
   NOTE: See dt-bindings/clock/numaker_m2l31x_clock.h
   NOTE: Check the link for requirement of 64-bit integer in zephyr
         https://docs.zephyrproject.org/latest/build/dts/intro-syntax-structure.html
4. Clock ontrol driver is soc-conditional on clock module index
5. Other drivers (gpio, serial, etc.) also must be soc-conditional on clock module index

Signed-off-by: Chun-Chieh Li <[email protected]>
ccli8 pushed a commit that referenced this pull request May 27, 2025
Current code does not build on Cortex-M0, seems like it does not like
subs:

Error: instruction not supported in Thumb16 mode -- `subs r3,#1'

Adding a unified assembler language declaration in the snippet seems to
fix the problem, also add an M0+ board so this is tested in CI.

Signed-off-by: Fabio Baltieri <[email protected]>
ccli8 pushed a commit that referenced this pull request Jun 26, 2025
Add possibility to perform crop on all pipes and compose (downscale) on
pixel pipes (endpoint #1 and endpoint #2).
Rework the code in order to move the downscale control from
the set_fmt into the set_selection (compose).

Signed-off-by: Alain Volmat <[email protected]>
ccli8 pushed a commit that referenced this pull request Sep 12, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420
(semi)planar formats which can be output by the main #1 pipe.

Signed-off-by: Alain Volmat <[email protected]>
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2 participants