Agilex™ 7 F-Tile AVST PCI Express* Configuration Intercept Interface (CII) Example Design

Table of Contents

• About This Document
• Overview
• CII Module Description
• Project Details
• Getting Started
• Viewing Results

About This Document

This document provides information about the F-Tile Avalon® Streaming IP for PCI Express Configuration Intercept Interface (CII) interface. The document details an example design that demonstrates CII use cases, including adds VPD capability and modifies max payload size, with F-tile Avalon® Streaming FPGA IP for PCI Express configured as a Gen4x16 endpoint using Quartus Prime Pro v25.1.1. It also details the steps for running the example design on Agilex™ 7 F-Series FPGA Development Kit board, and viewing the results using utilities like lspci and Signal Tap Logic Analyzer.

Target Audience

This document is intended for FPGA and system developers to use as a guide for evaluating the F-Tile AVST PCIe IP and CII interface on the Agilex™ 7 F-Series F-Tile FPGA Development Kit.

Terms and Acronyms

Terms	Description
AVST	Avalon® Streaming
CfgWr	Configuration Write request. A type of PCIe Transaction Layer Packet (TLP) that the host system generates to write data into the configuration space registers of a PCIe device.
CfgRd	Configuration Read request. A type of PCIe TLP that the host system generates to read data from the configuration space registers of a PCIe device.
CfgRd Completion	Configuration Read Completion. A type of PCIe TLP that the PCIe device generates in response to a Configuration Read (CfgRd) request from the host. It contains the requested data from the device's configuration space registers.
Configuration Space Header	The first 64 bytes of a Function's Configuration Space (Offset 00h - 3Fh). Capabilities Pointer register (Offset 34h) gives location of first register block in the linked list of Capability Structures in PCI-Compatible Configuration Space.
Linked list of Capabilities	PCIe Configuration Space Capabilities are linked together as a linked list. This is referred to as a capability chain in this document
PCI-Compatible Configuration Space	The first 256 bytes of a Function's Configuration Space (Offset 00h ~ FFh). PCI-Compatible Capability registers are located in this space. E.g., Power Management (ID: 01h), Vital Product Data (ID: 03h), PCI Express (ID: 10h)
PCI Express Extended Configuration Space	Configuration Space at offset 256 or greater (Offset 100h ~ FFFh). PCI Express Extended Capability registers are located in this space. E.g., Advance Error Reporting (AER) Capability (ID: 001h).
CII	Configuration Intercept Interface of F-Tile Avalon® Streaming IP for PCI Express. This interface allows the application logic to detect the occurrence of a CFG request on the link and to modify its behavior.
VPD	Vital Product Data Capability register. Includes information that uniquely identifies hardware and, potentially, software elements of a system.
Max payload size	This field in Device Control register (Offset 0x08h; bits[7:5]) sets maximum TLP payload size for the Function.

Related Information

• F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
• F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
• Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile)
• Quartus Prime Pro Signal Tap Logic Analyzer Tool

Overview

Agilex™ 7 F-Tile AVST PCIe IP CII interface allows the application logic to detect the occurrence of a Configuration (CFG) request from the host and modify its behavior. The application logic can use the CII to :

• Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first.
• Overwrite the data payload of a CfgWr request.
• Overwrite the data payload of a CfgRd Completion.

This example design is based on Quartus Prime Pro generated F-tile AVST PCIe Programmed Input/Output example design and an example CII module to demonstrate 2 CII use cases:

• A PCIe capability structure is added to the example design capability chain by modifying Capabilities Pointer through the CII interface.
• Value of PCI Express Capabilities register is updated by overwriting CfgWr data to the register.

The instantiated F-tile AVST PCIe example design allows the device to be configured as a Gen4x16 Endpoint and link up with a Gen4 host and enumerate the device in the system topology. The CII module adds the capability for intercepting CfgWr and CfgRd Completion requests.

Below is the block diagram of the example design.

F-Tile AVST PCIe IP Interface / Signal Description

The following tables describe the IP interface signals.

Clocks

Interface / Signal	Description
refclk0, refclk1	Input reference clock from F-Tile Reference and SystemPLL Clocks IP.
coreclkout_hip	This 500MHz clock drives the IP core application layer.
pcie_systempll_clk	System PLL clock from F-Tile Reference and SystemPLL Clocks IP.

For more info, refer to the IP User Guide.

• [Clocks] (https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/clocks-and-resets.html)

Resets

Interface / Signal	Description
pin_perst_n	Active low PCIe reset input to PCIe Hard IP for PERST# function defined by PCIe specification.
p0_pin_perst_n	PERST# status indication for port 0.
p0_reset_status_n	Active low reset status synchronized to coreclkout_hip.
ninit_done	Active low signal indicates the FPGA device has been configured and is in normal operating mode.

CII Interface

Interface / Signal	Description
p0_cii_*	Configuration Intercept Interface.

For more info, refer to the IP User Guide.

• [CII Interface] (https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/configuration-intercept-interface-ep-only-17056.html)

Avalon® Streaming TX Interface

Interface / Signal	Description
p0_tx_st*	Avalon® Streaming TX Interface.
p0_tx_cdts_limit*	TX Flow Control Interface.

For more info, refer to the IP User Guide.

• [Streaming TX Interface] (https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/avalon-st-tx-interface-signals.html)

Avalon® Streaming RX Interface

Interface / Signal	Description
p0_rx_st*	Avalon® Streaming RX Interface.

For more info, refer to the IP User Guide.

• [Streaming RX Interface] (https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/avalon-st-rx-interface-signals.html)

Serial Data Interface

Interface / Signal	Description
tx_p/n_out	Transmit serial data output using High Speed Differential I/O Standard.
rx_p/n_in	Receive serial data output using High Speed Differential I/O Standard.

For more info, refer to the IP User Guide.

• [Serial Data Interface] (https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/serial-data-interface.html)

CII Module Description

This example design demonstrate 2 CII use cases: (1) adding VPD cability and (2) update max payload size to 128 bytes.

F-tile AVST PCIe IP PIO example design Capability chain before VPD is being added:

Example design Capability register chain with VPD added:

Device Control register as part of PCI Express Capability Structure and max payload size field (bit[7:5]).

The CII module performs additional steps to intercept payload data of CfgWr and CfgRd Completion:

1. After reset, the CII module asserts cii_halt to 1.

2. The F-tile AVST PCIe IP intercepts the CFG requests and asserts cii_req along with other CII output signals.

3. On every CFG request (cii_req = 1), the CII module deasserts cii_halt for 1 clock cycle, allowing the request to completed.

   With the cii_halt deasserted:

   • If the CFG write (cii_wr = 1) data needs to be overwritten, assert cii_override_en and provide write data via cii_override_din[31:0]
   • If the CFG read (cii_wr = 0) completion data needs to be overwritten, assert cii_override_en and provide read data via cii_override_din[31:0]

4. For VPD capability use case, the CII module monitors the cii_addr[9:0] and overwrites the read data as follows:

   • cii_addr == 0x00d (Offset 0x34); cii_override_din = 0x0060
   • cii_addr == 0x018 (Offset 0x60); cii_override_din = 0x4003

5. For MPS update use case, the CII module monitors the cii_addr[9:0] and overwrites the write data as follows:

   • cii_addr == 0x01E (Offset 0x78); cii_override_din = 0x2910

   This will update the max payload size of the example design to 128 bytes (bit[7:5] = 0).

For details, refer to ip/cii.v.

F-tile AVST PCIe IP CII Parameter Setting

Top level settings:

Check Enable Configuration Interface Intercept option:

Project Details

• Family: Agilex™ 7
• Quartus Version: Quartus Prime Pro Software v. 25.1.1
• Development Kit: Agilex™ 7 FPGA F-Series Development Kit (2xF-tile), Ordering Code: DK-DEV-AGF023FA
• Device Part: AGFD023R24C2E1VC

Getting Started

Required Components for Hardware Testing

• FPGA Board.
  • Agilex™ 7 FPGA F-Series Development Kit (2xF-tile)
• Tools and software
  • Quartus ®Prime Pro Software

Below are the steps to compile the example design, test on hardware and view the result.

Compilation Steps

1. Open the Quartus project file (.qpf) in Quartus ®Prime Pro Software. Click File > Open Project, and select pcie_ed.qpf.
2. Click Processing > Start Compilation.

Hardware Testing Steps

The following instruction shows the steps to run the example design on Agilex™ 7 FPGA F-Series Development Kit.

1. Install Agilex™ 7 FPGA F-Series Development Kit on a host machine PCIe x16 slot.

2. Connect the micro-USB programming cable to J10. See below for J10 location.

   Reference: Board Overview

3. Apply power to the Development Kit. See below for details.

   Reference: Applying Power to the Development Board

4. Download the bitstream (pcie_ed.sof). See below for details.

   Reference: FPGA Configuration

5. Reboot the host machine

Viewing Results

Verify that the VPD Capability is shown in the lspci command output

On the host machine, run lspci command:

sudo lspci -d 1172: -v

Example Design Capability List: before adding the VPD (PIO Example design)

Example Design Capability List: after adding the VPD

Verify that max payload size is updated

On the host machine, run lspci command:

sudo lspci -d 1172: -vvv

MaxPayload value of PCI Express Device Control Register is updated to 128 bytes

Signal Tap Logic Analyzer Capture

You can also observe the CII interface signals in Signal Tap. Below are some examples of the Signal Tap capture.

Intercept CFG read and overwrite CFG read completion data:

Intercept CFG write and overwrite payload data: