Tweaks to make Verilator Happy #8
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When simulating the i2c master module under verilator, several linting errors occurred that this commit addresses. Specifically * Several types were of excessive length and were subject to vector length mismatch errors. * The PHY and controller state machines did not have a default case and do not cover the entire potential space, so a specious default was added to reset back to IDLE in the case of error.
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When simulating the i2c master module under verilator, several linting errors occurred that this commit addresses.
Specifically