Multi-Bit-Comparator

Author: Soham Kapur

Description: Variations of a generalized multi-bit/magnitude comparator with trade-offs among timing and area.

Tools Used: Verilog HDL, Xilinx Vivado, Altera Quartus

Concepts Used: Clock gating, Power gating, Area-Power-Timing trade-off, Comparator

Device Simulated: Cyclone IV E: EP4CE115F29C7

Multi Bit Comparator with Power Gating: 4-bit Comparator


Single Bit Comparator with Power Gating: Fmax = 103.69 MHz


Serialized Multi Bit Comparator: Fmax = 118.88 MHz