[Backport][6.6] IPIV-BUGFIX #14
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…eature Add ARM64_HISI_IPIV config to control whether enable the IPIV feature. The IPIV feature optimizes vSGI performance based on GICv4.1 and is a feature of HIP12. Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
IPIV uses ioctl to be enabled. Users (such as qemu) can invoke the ioctl to enable IPIV. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
Introduce a paravirtualization interface for KVM/arm64 to PV-sgi. A hypercall interface is provided for the guest to interrogate the hypervisor's support for IPIV. In the previous IPIV implementation, the MPIDR value of the vCPU needs to be changed to prevent guests from sending multicast and broadcast. This series of bugfix patches provide a method: Add the SMCCC interface to the kernel so that the guest OS can control the enabling of IPIV. When IPIV is enabled, the guest OS uses multiple unicast to implement multicast. (Broadcasting cannot be implemented due to hardware limitations. If a guest sends a broadcast, an exception message is displayed on the host.) In this way, do not need to modify the MPIDR. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
This provides a mechanism for querying whether IPIV are available in this hypervisor. Add some SMCCC compatible hypercalls for PV SGI: PV_SGI_FEATURES: 0xC6000090 PV_SGI_ENABLE: 0xC6000091 ipiv_enable is a global variable, indicating whether the hardware supports IPIV. enable_ipiv_from_vmm indicates whether the VMM (such as QEMU) enables IPIV through ioctl. enable_ipiv_from_guest indicates whether the guest OS enables IPIV through the SMCCC interface. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
Use the smccc interface to enable ipiv for the guest OS, modify the guest kernel, and use multiple unicasts to implement group boradcast. In this way, do not need to modify the MPIDR. In addition, the MPIDR modification is deleted, and the GICD configuration is modified. The hardware uses the mpidr to calculate the corresponding vCPU ID to lookup vpeid table. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
GITS_IIDR bit7 is used to store whether IPIV is enabled for Guest OS to ensure that enable_ipiv_from_guest are the same before and after live migration. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
… in IPIv When the VM's vgic is initialized, vpeids are written to vpeid table in the sequence of vcpu_idx. However, the actual hardware lookups vpeid_table in the sequence of vcpu_id. Therefore, ensure that vcpu_idx and vcpu_id are the same for IPIV. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
IPIV uses the MPIDR value to transmit vpeid to hardware, so don't allow to change it. Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
when kvm-arm.vgic_v4_enable=0 kvm-arm.ipiv_enabled=1 is configured in the cmdline, the Host KVM displays "ipiv enabled", but ipiv is not enabled. gic_data.rdists.has_rvpeid is hardware-level information, which does not indicate that GICv4.1 is enabled for KVM. So whether the host supports IPIV depends on KVM enables GICv4.1m instead of hardware supports GICv4.1. Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
Displays detailed IPIV error causes based on hardware information. 1. Guest sends SGI with IRM=1. 2. Guest sends multicast. 3. The index of VM table exceeds the supported range. Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
GICD_MISC_CTRL bit19(cfg_ipiv_en) is read-only in EL2. The write of GICD_MISC_CTRL bit19=1 is done by BIOS. Therefore, need to check whether the BIOS has enabled ipiv in OS. Fixes: 5aac9c6 ("downstream: kvm: hisi_virt: Probe and configure IPIV capacity on HIP12") Signed-off-by: Jinqian Yang <[email protected]> Signed-off-by: nzq-hw <[email protected]>
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