lcd: driver defect clean up

PD#150465: driver defect clean up:
torvalds#71
torvalds#77
torvalds#109
torvalds#127
torvalds#411
torvalds#600
torvalds#602
torvalds#603
torvalds#604
torvalds#611
torvalds#612

Change-Id: I38ac5ed6583bd6e57df9f42eaab04d05ee4ed663
Signed-off-by: Evoke Zhang <[email protected]>

Author: Evoke Zhang

drivers/amlogic/media/vout/lcd/lcd_clk_config.c

@@ -229,14 +229,16 @@ void lcd_clk_config_print(void)
 			"div_sel:      %s(index %d)\n"
 			"xd:           %d\n"
 			"fout:         %dkHz\n"
-			"ss_level:     %d\n\n",
+			"ss_level:     %d\n"
+			"pll_mode:     %d\n\n",
 			clk_conf.pll_m, clk_conf.pll_n,
 			clk_conf.pll_frac, clk_conf.pll_fvco,
 			clk_conf.pll_od1_sel, clk_conf.pll_od2_sel,
 			clk_conf.pll_od3_sel, clk_conf.pll_fout,
 			lcd_clk_div_sel_table[clk_conf.div_sel],
 			clk_conf.div_sel, clk_conf.xd,
-			clk_conf.fout, clk_conf.ss_level);
+			clk_conf.fout, clk_conf.ss_level,
+			clk_conf.pll_mode);
 		break;
 	}
 }
@@ -587,7 +589,10 @@ static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf)
 	lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl);
 	lcd_hiu_write(HHI_HDMI_PLL_CNTL2, pll_ctrl2);
 	lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3);
-	lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+	if (cConf->pll_mode)
+		lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x0d160000);
+	else
+		lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 	lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
 	lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
 	lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_TXL, 1);
@@ -1286,6 +1291,11 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf)
 		goto generate_clk_done_txl;
 	}
 
+	if (pconf->lcd_timing.clk_auto == 2)
+		cConf->pll_mode = 1;
+	else
+		cConf->pll_mode = 0;
+
 	switch (pconf->lcd_basic.lcd_type) {
 	case LCD_TTL:
 		clk_div_sel = CLK_DIV_SEL_1;

drivers/amlogic/media/vout/lcd/lcd_clk_config.h

@@ -21,7 +21,10 @@
 #include <linux/types.h>
 #include <linux/amlogic/media/vout/lcd/lcd_vout.h>
 
-/* clk config */
+/* **********************************
+ * clk config
+ * **********************************
+ */
 struct lcd_clk_config_s { /* unit: kHz */
 	/* IN-OUT parameters */
 	unsigned int fin;
@@ -69,9 +72,13 @@ struct lcd_clk_config_s { /* unit: kHz */
 	unsigned int div_out_fmax; /* g9tv, g9bb, gxbb */
 	unsigned int xd_out_fmax;
 	unsigned int err_fmin;
+	unsigned int pll_mode;
 };
 
-/* pll & clk parameter */
+/* **********************************
+ * pll & clk parameter
+ * **********************************
+ */
 /* ******** clk calculation ******** */
 #define PLL_WAIT_LOCK_CNT           200
  /* frequency unit: kHz */
@@ -110,7 +117,10 @@ enum div_sel_e {
 };
 
 
-/* GXTVBB */
+/* **********************************
+ * GXTVBB
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL 0x10c8 */
 #define LCD_PLL_LOCK_GXTVBB         31
@@ -143,7 +153,10 @@ enum div_sel_e {
 #define CRT_VID_CLK_IN_MAX_GXTVBB   (3100 * 1000)
 #define ENCL_CLK_IN_MAX_GXTVBB      (620 * 1000)
 
-/* GXL */
+/* **********************************
+ * GXL
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL 0x10c8 */
 #define LCD_PLL_LOCK_GXL            31
@@ -176,7 +189,10 @@ enum div_sel_e {
 #define CRT_VID_CLK_IN_MAX_GXL      (3100 * 1000)
 #define ENCL_CLK_IN_MAX_GXL         (620 * 1000)
 
-/* GXM */
+/* **********************************
+ * GXM
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL 0x10c8 */
 #define LCD_PLL_LOCK_GXM            31
@@ -209,7 +225,10 @@ enum div_sel_e {
 #define CRT_VID_CLK_IN_MAX_GXM      (3100 * 1000)
 #define ENCL_CLK_IN_MAX_GXM         (620 * 1000)
 
-/* TXL */
+/* **********************************
+ * TXL
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL 0x10c8 */
 #define LCD_PLL_LOCK_TXL            31
@@ -242,7 +261,10 @@ enum div_sel_e {
 #define CRT_VID_CLK_IN_MAX_TXL      (3100 * 1000)
 #define ENCL_CLK_IN_MAX_TXL         (620 * 1000)
 
-/*  TXLX */
+/* **********************************
+ * TXLX
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL 0x10c8 */
 #define LCD_PLL_LOCK_TXLX            31
@@ -275,7 +297,10 @@ enum div_sel_e {
 #define CRT_VID_CLK_IN_MAX_TXLX      (3100 * 1000)
 #define ENCL_CLK_IN_MAX_TXLX         (620 * 1000)
 
-/* AXG */
+/* **********************************
+ * AXG
+ * **********************************
+ */
 /* ******** register bit ******** */
 /* PLL_CNTL */
 #define LCD_PLL_LOCK_AXG            31

drivers/amlogic/media/vout/lcd/lcd_common.c

@@ -38,7 +38,10 @@
 #include "lcd_common.h"
 #include "lcd_reg.h"
 
-/* lcd type */
+/* **********************************
+ * lcd type
+ * **********************************
+ */
 struct lcd_type_match_s {
 	char *name;
 	enum lcd_type_e type;
@@ -102,7 +105,10 @@ char *lcd_mode_mode_to_str(int mode)
 	return lcd_mode_table[mode];
 }
 
-/* lcd gpio */
+/* **********************************
+ * lcd gpio
+ * **********************************
+ */
 #if 0
 #define lcd_gpio_request(dev, str)        gpiod_get(dev, str)
 #define lcd_gpio_free(gdesc)              gpiod_put(gdesc)
@@ -780,17 +786,17 @@ int lcd_vmode_change(struct lcd_config_s *pconf)
 	char str[100];
 	int len = 0;
 
-	pconf->lcd_timing.clk_change = 0; /* clear clk flga */
+	pconf->lcd_timing.clk_change = 0; /* clear clk flag */
 	switch (type) {
 	case 0: /* pixel clk adjust */
 		pclk = (h_period * v_period) / duration_den * duration_num;
 		if (pconf->lcd_timing.lcd_clk != pclk)
 			pconf->lcd_timing.clk_change = LCD_CLK_PLL_CHANGE;
 		break;
 	case 1: /* htotal adjust */
-		h_period = ((pclk / v_period) * duration_den * 10) /
+		h_period = ((pclk / v_period) * duration_den * 100) /
 				duration_num;
-		h_period = (h_period + 5) / 10; /* round off */
+		h_period = (h_period + 99) / 100; /* round off */
 		if (pconf->lcd_basic.h_period != h_period) {
 			/* check clk frac update */
 			pclk = (h_period * v_period) / duration_den *
@@ -802,9 +808,9 @@ int lcd_vmode_change(struct lcd_config_s *pconf)
 		}
 		break;
 	case 2: /* vtotal adjust */
-		v_period = ((pclk / h_period) * duration_den * 10) /
+		v_period = ((pclk / h_period) * duration_den * 100) /
 				duration_num;
-		v_period = (v_period + 5) / 10; /* round off */
+		v_period = (v_period + 99) / 100; /* round off */
 		if (pconf->lcd_basic.v_period != v_period) {
 			/* check clk frac update */
 			pclk = (h_period * v_period) / duration_den *
@@ -817,14 +823,14 @@ int lcd_vmode_change(struct lcd_config_s *pconf)
 		break;
 	case 3: /* free adjust, use min/max range to calculate */
 	default:
-		v_period = ((pclk / h_period) * duration_den * 10) /
+		v_period = ((pclk / h_period) * duration_den * 100) /
 			duration_num;
-		v_period = (v_period + 5) / 10; /* round off */
+		v_period = (v_period + 99) / 100; /* round off */
 		if (v_period > pconf->lcd_basic.v_period_max) {
 			v_period = pconf->lcd_basic.v_period_max;
-			h_period = ((pclk / v_period) * duration_den * 10) /
+			h_period = ((pclk / v_period) * duration_den * 100) /
 				duration_num;
-			h_period = (h_period + 5) / 10; /* round off */
+			h_period = (h_period + 99) / 100; /* round off */
 			if (h_period > pconf->lcd_basic.h_period_max) {
 				h_period = pconf->lcd_basic.h_period_max;
 				pclk = (h_period * v_period) / duration_den *
@@ -841,9 +847,9 @@ int lcd_vmode_change(struct lcd_config_s *pconf)
 			}
 		} else if (v_period < pconf->lcd_basic.v_period_min) {
 			v_period = pconf->lcd_basic.v_period_min;
-			h_period = ((pclk / v_period) * duration_den * 10) /
+			h_period = ((pclk / v_period) * duration_den * 100) /
 				duration_num;
-			h_period = (h_period + 5) / 10; /* round off */
+			h_period = (h_period + 99) / 100; /* round off */
 			if (h_period < pconf->lcd_basic.h_period_min) {
 				h_period = pconf->lcd_basic.h_period_min;
 				pclk = (h_period * v_period) / duration_den *

drivers/amlogic/media/vout/lcd/lcd_common.h

@@ -23,7 +23,8 @@
 #include "lcd_clk_config.h"
 
 /* 20170505: add a113 support to linux4.9 */
-#define LCD_DRV_VERSION    "20170505"
+/* 20170905: fix coverity errors */
+#define LCD_DRV_VERSION    "20170905"
 
 #define VPP_OUT_SATURATE            (1 << 0)