diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx
new file mode 100644
index 0000000000000..1210383f34ec5
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx
@@ -0,0 +1,20 @@
+# Kconfig - ST Microelectronics STM32L432KC MCU
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32L432XX
+
+config SOC
+	string
+	default stm32l432xx
+
+config NUM_IRQS
+	int
+	default 82
+
+endif # SOC_STM32L432XX
+
diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
index 69f80ebc27e21..e636253663df4 100644
--- a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
+++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
@@ -14,6 +14,10 @@ config SOC_STM32L476XX
 	bool "STM32L476XX"
 	select HAS_STM32CUBE
 
+config SOC_STM32L432XX
+	bool "STM32L432XX"
+	select HAS_STM32CUBE
+
 config SOC_STM32L475XG
 	bool "STM32L475XG"
 	select HAS_STM32CUBE
diff --git a/boards/arm/nucleo_l432kc/Kconfig.board b/boards/arm/nucleo_l432kc/Kconfig.board
new file mode 100644
index 0000000000000..5d3573d9f5c1e
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/Kconfig.board
@@ -0,0 +1,11 @@
+# Kconfig - STM32L432KC Nucleo board configuration
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_NUCLEO_L432KC
+	bool "Nucleo L432KC Development Board"
+	depends on SOC_STM32L432XX
diff --git a/boards/arm/nucleo_l432kc/Kconfig.defconfig b/boards/arm/nucleo_l432kc/Kconfig.defconfig
new file mode 100644
index 0000000000000..8042239432584
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/Kconfig.defconfig
@@ -0,0 +1,14 @@
+# Kconfig - STM32L432KC Nucleo board configuration
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_NUCLEO_L432KC
+
+config BOARD
+	default nucleo_l432kc
+
+endif # BOARD_NUCLEO_L432KC
diff --git a/boards/arm/nucleo_l432kc/Makefile b/boards/arm/nucleo_l432kc/Makefile
new file mode 100644
index 0000000000000..c925263c43a73
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/Makefile
@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o
diff --git a/boards/arm/nucleo_l432kc/board.h b/boards/arm/nucleo_l432kc/board.h
new file mode 100644
index 0000000000000..4449a25671cd6
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/board.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* LD3 green LED */
+#define LD3_GPIO_PORT	"GPIOB"
+#define LD3_GPIO_PIN	3
+
+/* Create aliases to make the basic samples work */
+#define LED0_GPIO_PORT	LD3_GPIO_PORT
+#define LED0_GPIO_PIN	LD3_GPIO_PIN
+
+#endif /* __INC_BOARD_H */
diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo32_ulp_logo.jpg b/boards/arm/nucleo_l432kc/doc/img/nucleo32_ulp_logo.jpg
new file mode 100644
index 0000000000000..6be9bdb367e0d
Binary files /dev/null and b/boards/arm/nucleo_l432kc/doc/img/nucleo32_ulp_logo.jpg differ
diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.png b/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.png
new file mode 100644
index 0000000000000..bb9a3d995914f
Binary files /dev/null and b/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.png differ
diff --git a/boards/arm/nucleo_l432kc/doc/nucleol432kc.rst b/boards/arm/nucleo_l432kc/doc/nucleol432kc.rst
new file mode 100644
index 0000000000000..fe3d0e137fde5
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/doc/nucleol432kc.rst
@@ -0,0 +1,237 @@
+.. _nucleo_l432kc_board:
+
+ST Nucleo L432KC
+################
+
+Overview
+********
+
+The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU
+with a wide range of connectivity support and configurations. Here are
+some highlights of the Nucleo L432KC board:
+
+- STM32 microcontroller in UFQFPN32 package
+- Arduino Uno V3 connectivity
+- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
+- Flexible board power supply:
+
+       - USB VBUS or external source(3.3V, 5V, 7 - 12V)
+       - Power management access point
+
+- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3)
+- One push-button: RESET
+
+.. image:: img/nucleo32_ulp_logo.jpg
+     :width: 250px
+     :align: center
+     :height: 188px
+     :alt: Nucleo L432KC
+
+More information about the board can be found at the `Nucleo L432KC website`_.
+
+Hardware
+********
+
+The STM32L432KC SoC provides the following hardware IPs:
+
+- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 μA/MHz run mode)
+- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
+- Clock Sources:
+
+        - 32 kHz crystal oscillator for RTC (LSE)
+        - Internal 16 MHz factory-trimmed RC (±1%)
+        - Internal low-power 32 kHz RC (±5%)
+        - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
+        - 2 PLLs for system clock, USB, audio, ADC
+
+- RTC with HW calendar, alarms and calibration
+- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors
+- 11x timers:
+
+        - 1x 16-bit advanced motor-control
+        - 1x 32-bit and 2x 16-bit general purpose
+        - 2x 16-bit basic
+        - 2x low-power 16-bit timers (available in Stop mode)
+        - 2x watchdogs
+        - SysTick timer
+
+- Up to 26 fast I/Os, most 5 V-tolerant
+- Memories
+
+        - Up to 256 KB single bank Flash, proprietary code readout protection
+        - Up to 64 KB of SRAM including 16 KB with hardware parity check
+        - Quad SPI memory interface
+
+- Rich analog peripherals (independent supply)
+
+        - 1× 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 μA/MSPS
+        - 2x 12-bit DAC, low-power sample and hold
+        - 1x operational amplifiers with built-in PGA
+        - 2x ultra-low-power comparators
+
+- 13x communication interfaces
+
+        - USB OTG 2.0 full-speed crystal less solution with LPM and BCD
+        - 1x SAIs (serial audio interface)
+        - 2x I2C FM+(1 Mbit/s), SMBus/PMBus
+        - 3x USARTs (ISO 7816, LIN, IrDA, modem)
+        - 2x SPIs (3x SPIs with the Quad SPI)
+        - CAN (2.0B Active)
+        - SWPMI single wire protocol master I/F
+        - IRTIM (Infrared interface)
+
+- 14-channel DMA controller
+- True random number generator
+- CRC calculation unit, 96-bit unique ID
+- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
+
+
+More information about STM32L432KC can be found here:
+       - `STM32L432KC on www.st.com`_
+       - `STM32L432 reference manual`_
+
+Supported Features
+==================
+
+The Zephyr nucleo_l432kc board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+
+	``boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig``
+
+
+Connections and IOs
+===================
+
+Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Available pins:
+---------------
+.. image:: img/nucleo_l432kc_arduino_nano.png
+     :width: 960px
+     :align: center
+     :height: 720px
+     :alt: Nucleo L432KC Arduino connectors
+
+For mode details please refer to `STM32 Nucleo-32 board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART_1_TX : PA9
+- UART_1_RX : PA10
+- UART_2_TX : PA2
+- UART_2_RX : PA3
+- I2C_1_SCL : PB6
+- I2C_1_SDA : PB7
+- PWM_2_CH1 : PA0
+- LD3 : PB3
+
+System Clock
+------------
+
+Nucleo L432KC System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
+driven by 16MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2.
+Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool interface.
+This interface is not supported by the openocd version 0.9 included by the Zephyr SDK v0.9.
+Until we update the Zephyr SDK, use openocd v0.10.0 from the openocd-stm32 project on GitHub
+to get the minimum set of scripts needed to flash and debug STM32 development boards.
+
+.. code-block:: console
+
+   $ git clone  https://github.com/erwango/openocd-stm32.git
+
+Then follow instructions in README.md
+
+
+Flashing an application to Nucleo L432KC
+----------------------------------------
+
+The sample application :ref:`hello_world` is being used in this tutorial:
+
+To build the Zephyr kernel and application, enter:
+
+.. code-block:: console
+
+   $ cd <zephyr_root_path>
+   $ source zephyr-env.sh
+   $ cd $ZEPHYR_BASE/samples/hello_world/
+   $ make BOARD=nucleo_l432kc
+
+Connect the Nucleo L432KC to your host computer using the USB port.
+Then, enter the following command:
+
+.. code-block:: console
+
+   $ cd <openocd-stm32_path>
+   $ stm32_flsh l4 $ZEPHYR_BASE/samples/hello_world/outdir/nucleo_l432kc/zephyr.bin
+
+Run a serial host program to connect with your Nucleo board.
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+You should see the following message:
+
+.. code-block:: console
+
+   $ Hello World! arm
+
+
+Debugging
+=========
+
+Access gdb with the following make command:
+
+.. code-block:: console
+
+   $ cd <openocd-stm32_path>
+   $ stm32_dbg l4 $ZEPHYR_BASE/samples/hello_world/outdir/nucleo_l432kc/zephyr.elf
+
+.. _Nucleo L432KC website:
+   http://www.st.com/en/evaluation-tools/nucleo-l432kc.html
+
+.. _STM32 Nucleo-32 board User Manual:
+   http://www.st.com/resource/en/user_manual/dm00231744.pdf
+
+.. _STM32L432KC on www.st.com:
+   http://www.st.com/en/microcontrollers/stm32l432kc.html
+
+.. _STM32L432 reference manual:
+   http://www.st.com/resource/en/reference_manual/dm00151940.pdf
diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig b/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig
new file mode 100644
index 0000000000000..0a63d14e2332c
--- /dev/null
+++ b/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_BOARD_STM32_NUCLEO_L432KC=y
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32L4X=y
+CONFIG_SOC_STM32L432XX=y
+CONFIG_CORTEX_M_SYSTICK=y
+# 80MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_STM32=y
+CONFIG_UART_STM32_PORT_2=y
+
+# enable pinmux
+CONFIG_PINMUX=y
+CONFIG_PINMUX_STM32=y
+
+# enable GPIOs
+CONFIG_GPIO=y
+CONFIG_GPIO_STM32=y
+CONFIG_GPIO_STM32_PORTA=y
+CONFIG_GPIO_STM32_PORTB=y
+CONFIG_GPIO_STM32_PORTC=y
+CONFIG_GPIO_STM32_PORTH=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_STM32_CUBE=y
+# SYSCLK selection
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# PLL configuration
+CONFIG_CLOCK_STM32_PLL_SRC_HSI
+# produce 80MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
+CONFIG_CLOCK_STM32_PLL_R_DIVISOR=4
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=1
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
+
+#enable pwm
+CONFIG_PWM=y
+CONFIG_PWM_STM32=y
+CONFIG_PWM_STM32_2=y
+
+#enable DTS
+CONFIG_HAS_DTS=y
diff --git a/drivers/pinmux/Makefile b/drivers/pinmux/Makefile
index 95f20ebbdc98c..b50ac5fd66ceb 100644
--- a/drivers/pinmux/Makefile
+++ b/drivers/pinmux/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_BOARD_NUCLEO_F401RE) += stm32/pinmux_board_nucleo_f401re.o
 obj-$(CONFIG_BOARD_NUCLEO_F411RE) += stm32/pinmux_board_nucleo_f411re.o
 obj-$(CONFIG_BOARD_96B_CARBON) += stm32/pinmux_board_carbon.o
 obj-$(CONFIG_BOARD_NUCLEO_L476RG) += stm32/pinmux_board_nucleo_l476rg.o
+obj-$(CONFIG_BOARD_NUCLEO_L432KC) += stm32/pinmux_board_nucleo_l432kc.o
 obj-$(CONFIG_BOARD_DISCO_L475_IOT1) += stm32/pinmux_board_disco_l475_iot1.o
 obj-$(CONFIG_BOARD_OLIMEXINO_STM32) += stm32/pinmux_board_olimexino_stm32.o
 obj-$(CONFIG_BOARD_STM32_MINI_A15) += stm32/pinmux_board_stm32_mini_a15.o
diff --git a/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c b/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c
new file mode 100644
index 0000000000000..9ee4e4a48f11f
--- /dev/null
+++ b/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+#include "pinmux/pinmux.h"
+
+#include "pinmux_stm32.h"
+
+/* pin assignments for NUCLEO-L432KC board */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_STM32_PORT_1
+	{STM32_PIN_PA9,  STM32L4X_PINMUX_FUNC_PA9_USART1_TX},
+	{STM32_PIN_PA10, STM32L4X_PINMUX_FUNC_PA10_USART1_RX},
+#endif	/* CONFIG_UART_STM32_PORT_1 */
+#ifdef CONFIG_UART_STM32_PORT_2
+	{STM32_PIN_PA2, STM32L4X_PINMUX_FUNC_PA2_USART2_TX},
+	{STM32_PIN_PA3, STM32L4X_PINMUX_FUNC_PA3_USART2_RX},
+#endif	/* CONFIG_UART_STM32_PORT_2 */
+#ifdef CONFIG_I2C_1
+	{STM32_PIN_PB6, STM32L4X_PINMUX_FUNC_PB6_I2C1_SCL},
+	{STM32_PIN_PB7, STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA},
+#endif /* CONFIG_I2C_1 */
+#ifdef CONFIG_PWM_STM32_2
+	{STM32_PIN_PA0, STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1},
+#endif /* CONFIG_PWM_STM32_2 */
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
+	 CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
diff --git a/drivers/pinmux/stm32/pinmux_stm32.c b/drivers/pinmux/stm32/pinmux_stm32.c
index 0fe6abd013625..1f699a8173d8e 100644
--- a/drivers/pinmux/stm32/pinmux_stm32.c
+++ b/drivers/pinmux/stm32/pinmux_stm32.c
@@ -28,7 +28,9 @@ static const u32_t ports_enable[STM32_PORTS_MAX] = {
 	STM32_PERIPH_GPIOA,
 	STM32_PERIPH_GPIOB,
 	STM32_PERIPH_GPIOC,
+#ifdef GPIOD_BASE
 	STM32_PERIPH_GPIOD,
+#endif
 #ifdef GPIOE_BASE
 	STM32_PERIPH_GPIOE,
 #endif
diff --git a/dts/arm/Makefile b/dts/arm/Makefile
index 28cb52236cc14..80e6350212c1c 100644
--- a/dts/arm/Makefile
+++ b/dts/arm/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_BOARD_HEXIWEAR_KW40Z)	=	hexiwear_kw40z.dts_compiled
 dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL)	=	cc3200_launchxl.dts_compiled
 dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL)	=	cc3220sf_launchxl.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_L476RG)	=	nucleo_l476rg.dts_compiled
+dtb-$(CONFIG_BOARD_NUCLEO_L432KC)	=	nucleo_l432kc.dts_compiled
 dtb-$(CONFIG_BOARD_V2M_BEETLE)		=	v2m_beetle.dts_compiled
 dtb-$(CONFIG_BOARD_OLIMEXINO_STM32)	=	olimexino_stm32.dts_compiled
 dtb-$(CONFIG_BOARD_96B_CARBON)		=	96b_carbon.dts_compiled
diff --git a/dts/arm/nucleo_l432kc.dts b/dts/arm/nucleo_l432kc.dts
new file mode 100644
index 0000000000000..d32150c9eff38
--- /dev/null
+++ b/dts/arm/nucleo_l432kc.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/stm32l432.dtsi>
+
+/ {
+	model = "STMicroelectronics STM32L432KC-NUCLEO board";
+	compatible = "st,stm32l432kc-nucleo", "st,stm32l432";
+
+	chosen {
+		zephyr,console = &usart2;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart2 {
+	current-speed = <115200>;
+	status = "ok";
+};
diff --git a/dts/arm/nucleo_l432kc.fixup b/dts/arm/nucleo_l432kc.fixup
new file mode 100644
index 0000000000000..fd4984234556c
--- /dev/null
+++ b/dts/arm/nucleo_l432kc.fixup
@@ -0,0 +1,27 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS	ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_1_BAUD_RATE	ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_1_IRQ_PRI	ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define PORT_1_IRQ				ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define PORT_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define PORT_3_IRQ				ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS	ST_STM32_USART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_4_BAUD_RATE	ST_STM32_USART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_4_IRQ_PRI	ST_STM32_USART_40004C00_IRQ_0_PRIORITY
+#define PORT_4_IRQ				ST_STM32_USART_40004C00_IRQ_0
diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h
index b9628bafebfef..98e8713ce0dbe 100644
--- a/dts/arm/st/mem.h
+++ b/dts/arm/st/mem.h
@@ -39,6 +39,9 @@
 #elif defined(CONFIG_SOC_STM32L476XX)
 #define DT_FLASH_SIZE		__SIZE_K(1024)
 #define DT_SRAM_SIZE		__SIZE_K(96)
+#elif defined(CONFIG_SOC_STM32L432XX)
+#define DT_FLASH_SIZE		__SIZE_K(256)
+#define DT_SRAM_SIZE		__SIZE_K(64)
 #else
 #error "Flash and RAM sizes not defined for this chip"
 #endif
diff --git a/dts/arm/st/stm32l432.dtsi b/dts/arm/st/stm32l432.dtsi
new file mode 100644
index 0000000000000..1b3c7bee59f0f
--- /dev/null
+++ b/dts/arm/st/stm32l432.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <st/mem.h>
+
+/ {
+	flash0: flash {
+		reg = <0x08000000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory {
+		reg = <0x20000000 DT_SRAM_SIZE>;
+	};
+
+	soc {
+		usart1: uart@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			interrupts = <37 0>;
+			status = "disabled";
+		};
+
+		usart2: uart@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38 0>;
+			status = "disabled";
+		};
+
+		usart3: uart@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39 0>;
+			status = "disabled";
+		};
+
+		uart4: uart@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};