modules: nrf_wifi: Add generic read/write APIs

These can be used read/write any address.

Signed-off-by: Chaitanya Tata <[email protected]>

Author: krish2718

include/zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h

@@ -98,6 +98,26 @@ int qspi_RDSR1(const struct device *dev, uint8_t *rdsr1);
 int qspi_RDSR2(const struct device *dev, uint8_t *rdsr2);
 int qspi_WRSR2(const struct device *dev, const uint8_t wrsr2);
 
+/**
+ * @brief Read a register via QSPI
+ *
+ * @param dev QSPI device
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int qspi_read_reg(const struct device *dev, uint8_t reg_addr, uint8_t *reg_value);
+
+/**
+ * @brief Write a register via QSPI
+ *
+ * @param dev QSPI device
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int qspi_write_reg(const struct device *dev, uint8_t reg_addr, uint8_t reg_value);
+
 #ifdef CONFIG_NRF_WIFI_LOW_POWER
 int func_rpu_sleep(void);
 int func_rpu_wake(void);

include/zephyr/drivers/wifi/nrf_wifi/bus/rpu_hw_if.h

@@ -54,6 +54,24 @@ int rpu_rdsr2(void);
 int rpu_rdsr1(void);
 int rpu_clks_on(void);
 
+/**
+ * @brief Read a register via RPU hardware interface
+ *
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int rpu_read_reg(uint8_t reg_addr, uint8_t *reg_value);
+
+/**
+ * @brief Write a register via RPU hardware interface
+ *
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int rpu_write_reg(uint8_t reg_addr, uint8_t reg_value);
+
 int rpu_init(void);
 int rpu_enable(void);
 int rpu_disable(void);

modules/nrf_wifi/bus/qspi_if.c

@@ -1190,6 +1190,85 @@ int qspi_cmd_wakeup_rpu(const struct device *dev, uint8_t data)
 	return ret;
 }
 
+/**
+ * @brief Read a register via QSPI
+ *
+ * @param dev QSPI device
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int qspi_read_reg(const struct device *dev, uint8_t reg_addr, uint8_t *reg_value)
+{
+	int ret = 0;
+	uint8_t sr = 0;
+
+	const struct qspi_buf sr_buf = {
+		.buf = &sr,
+		.len = sizeof(sr),
+	};
+	struct qspi_cmd cmd = {
+		.op_code = reg_addr,
+		.rx_buf = &sr_buf,
+	};
+
+	ret = qspi_device_init(dev);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = qspi_send_cmd(dev, &cmd, false);
+
+	qspi_device_uninit(dev);
+
+	LOG_DBG("QSPI read reg 0x%02x = 0x%02x", reg_addr, sr);
+
+	if (ret == 0) {
+		*reg_value = sr;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Write a register via QSPI
+ *
+ * @param dev QSPI device
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int qspi_write_reg(const struct device *dev, uint8_t reg_addr, uint8_t reg_value)
+{
+	int ret = 0;
+
+	const struct qspi_buf tx_buf = {
+		.buf = &reg_value,
+		.len = sizeof(reg_value),
+	};
+	const struct qspi_cmd cmd = {
+		.op_code = reg_addr,
+		.tx_buf = &tx_buf,
+	};
+
+	ret = qspi_device_init(dev);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = qspi_send_cmd(dev, &cmd, false);
+
+	qspi_device_uninit(dev);
+
+	LOG_DBG("QSPI write reg 0x%02x = 0x%02x", reg_addr, reg_value);
+
+	if (ret < 0) {
+		LOG_ERR("QSPI write reg 0x%02x failed: %d", reg_addr, ret);
+	}
+
+	return ret;
+}
+
 struct device qspi_perip = {
 	.data = &qspi_nor_memory_data,
 };

modules/nrf_wifi/bus/rpu_hw_if.c

@@ -429,6 +429,37 @@ int rpu_rdsr1(void)
 #endif
 }
 
+/**
+ * @brief Read a register via RPU hardware interface
+ *
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int rpu_read_reg(uint8_t reg_addr, uint8_t *reg_value)
+{
+#if CONFIG_NRF70_ON_QSPI
+	return qspi_read_reg(&qspi_perip, reg_addr, reg_value);
+#else
+	return spim_read_reg_wrapper(NULL, reg_addr, reg_value);
+#endif
+}
+
+/**
+ * @brief Write a register via RPU hardware interface
+ *
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int rpu_write_reg(uint8_t reg_addr, uint8_t reg_value)
+{
+#if CONFIG_NRF70_ON_QSPI
+	return qspi_write_reg(&qspi_perip, reg_addr, reg_value);
+#else
+	return spim_write_reg_wrapper(NULL, reg_addr, reg_value);
+#endif
+}
 
 int rpu_clks_on(void)
 {

modules/nrf_wifi/bus/spi_if.c

@@ -156,6 +156,34 @@ int spim_WRSR2(const struct device *dev, const uint8_t wrsr2)
 	return spim_write_reg(&spi_spec, 0x3F, wrsr2);
 }
 
+/**
+ * @brief Read a register via SPI (wrapper for compatibility)
+ *
+ * @param dev SPI device (unused, kept for compatibility)
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_read_reg_wrapper(const struct device *dev, uint8_t reg_addr, uint8_t *reg_value)
+{
+	ARG_UNUSED(dev);
+	return spim_read_reg(reg_addr, reg_value);
+}
+
+/**
+ * @brief Write a register via SPI (wrapper for compatibility)
+ *
+ * @param dev SPI device (unused, kept for compatibility)
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_write_reg_wrapper(const struct device *dev, uint8_t reg_addr, uint8_t reg_value)
+{
+	ARG_UNUSED(dev);
+	return spim_write_reg(&spi_spec, reg_addr, reg_value);
+}
+
 int _spim_wait_while_rpu_awake(void)
 {
 	int ret;

modules/nrf_wifi/bus/spi_if.h

@@ -9,6 +9,8 @@
  * Zephyr OS layer of the Wi-Fi driver.
  */
 
+#include <zephyr/drivers/spi.h>
+
 /* SPIM driver config */
 
 int spim_init(struct qspi_config *config);
@@ -34,3 +36,42 @@ int spim_RDSR1(const struct device *dev, uint8_t *rdsr1);
 int spim_RDSR2(const struct device *dev, uint8_t *rdsr2);
 
 int spim_WRSR2(const struct device *dev, const uint8_t wrsr2);
+
+/**
+ * @brief Read a register via SPI
+ *
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_read_reg(uint32_t reg_addr, uint8_t *reg_value);
+
+/**
+ * @brief Write a register via SPI
+ *
+ * @param spi_spec SPI device specification
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_write_reg(const struct spi_dt_spec *spi_spec, uint32_t reg_addr, const uint8_t reg_value);
+
+/**
+ * @brief Read a register via SPI (wrapper for compatibility)
+ *
+ * @param dev SPI device (unused, kept for compatibility)
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Pointer to store the read value
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_read_reg_wrapper(const struct device *dev, uint8_t reg_addr, uint8_t *reg_value);
+
+/**
+ * @brief Write a register via SPI (wrapper for compatibility)
+ *
+ * @param dev SPI device (unused, kept for compatibility)
+ * @param reg_addr Register address (opcode)
+ * @param reg_value Value to write
+ * @return int 0 on success, negative error code on failure
+ */
+int spim_write_reg_wrapper(const struct device *dev, uint8_t reg_addr, uint8_t reg_value);