tests: Add basic test-set for OpenRISC architecture port

The OpenRISC 1000 architecture can be tested through the qemu_or1k emulated
SoC and board. Because this emulated device has minimal external hardware
by default, this patch enables a minimal suite of tests covering core
kernel features for the CPU architecture.

When running the test suite, OpenRISC was found to require additional stack
space to prevent an overflow. Therefore, a minimal additional amount of
storage: 128-bytes, was added that was found in practice to allow tests to
complete.

Note that Qemu version 9.2.0 or newer is required so as to include the
following commit:

    commit 3eb43aeb164f1f83c97ff693c7d464b49755110c
    Author: Joel Holdsworth <[email protected]>
    Date:   Fri Jun 7 15:29:33 2024 -0700

        hw/openrisc: Fixed undercounting of TTCR in continuous mode

This fixes a bug in the implementation of the emulated OpenRISC Tick Timer
which prevents the Zephyr OpenRISC port from task-scheduling properly.

Signed-off-by: Joel Holdsworth <[email protected]>

Author: jhol

subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h

@@ -178,6 +178,8 @@ extern "C" {
 #define PROCESSOR_NAME "xtensa"
 #elif defined(CONFIG_SPARC)
 #define PROCESSOR_NAME "sparc"
+#elif defined(CONFIG_OPENRISC)
+#define PROCESSOR_NAME "openrisc"
 #endif
 
 #ifndef PROCESSOR_NAME

subsys/testsuite/Kconfig

@@ -18,6 +18,7 @@ config TEST_EXTRA_STACK_SIZE
 	int "Test function extra thread stack size"
 	default 2048 if COVERAGE_GCOV
 	default 768 if XTENSA
+	default 128 if OPENRISC
 	default 0
 	depends on TEST
 	help

subsys/testsuite/include/zephyr/interrupt_util.h

@@ -233,6 +233,14 @@ static inline void trigger_irq(int irq)
 	z_mips_enter_irq(irq);
 }
 
+#elif defined(CONFIG_OPENRISC)
+extern void z_openrisc_enter_irq(int);
+
+static inline void trigger_irq(int irq)
+{
+	z_openrisc_enter_irq(irq);
+}
+
 #elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM)
 
 extern void z_vim_arm_enter_irq(int);

subsys/testsuite/include/zephyr/test_asm_inline_gcc.h

@@ -48,6 +48,8 @@ static inline void timestamp_serialize(void)
 #define timestamp_serialize()
 #elif defined(CONFIG_RX)
 #define timestamp_serialize()
+#elif defined(CONFIG_OPENRISC)
+#define timestamp_serialize()
 #else
 #error implementation of timestamp_serialize() not provided for your CPU target
 #endif

tests/kernel/context/src/main.c

@@ -56,6 +56,7 @@
  */
 #elif defined(CONFIG_SPARC)
 #elif defined(CONFIG_MIPS)
+#elif defined(CONFIG_OPENRISC)
 #elif defined(CONFIG_ARCH_POSIX)
 #if defined(CONFIG_BOARD_NATIVE_SIM)
 #define TICK_IRQ TIMER_TICK_IRQ

tests/kernel/fatal/exception/src/main.c

@@ -122,6 +122,8 @@ void entry_cpu_exception_extend(void *p1, void *p2, void *p3)
 	 */
 #elif defined(CONFIG_ARC)
 	__asm__ volatile ("swi");
+#elif defined(CONFIG_OPENRISC)
+	__asm__ volatile ("l.trap 0");
 #else
 	/* used to create a divide by zero error on X86 and MIPS */
 	volatile int error;

tests/kernel/fatal/no-multithreading/testcase.yaml

@@ -4,6 +4,7 @@ common:
     - qemu_arc/qemu_arc_em
     - qemu_arc/qemu_arc_hs
     - qemu_arc/qemu_arc_hs6x
+    - qemu_or1k
     - qemu_riscv32
     - qemu_riscv32e
     - qemu_riscv64

tests/kernel/mem_slab/mslab_api/testcase.yaml

@@ -23,6 +23,7 @@ tests:
       - qemu_riscv32e
       - qemu_riscv64
       - qemu_leon3
+      - qemu_or1k
     integration_platforms:
       - qemu_cortex_m3
       - qemu_arc/qemu_arc_hs

tests/kernel/threads/no-multithreading/testcase.yaml

@@ -20,6 +20,7 @@ tests:
       - qemu_arc/qemu_arc_em
       - qemu_arc/qemu_arc_hs
       - qemu_arc/qemu_arc_hs6x
+      - qemu_or1k
       - qemu_riscv32
       - qemu_riscv32e
       - qemu_riscv64

tests/kernel/timer/timer_api/testcase.yaml

@@ -20,6 +20,7 @@ tests:
       - qemu_arc/qemu_arc_hs
       - qemu_arc/qemu_arc_hs6x
       - qemu_leon3
+      - qemu_or1k
     integration_platforms:
       - qemu_cortex_m3
       - nsim/nsim_em