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hal: renesas: rzt: Add SPI support for RZ/T series
Add SPI FSP HAL driver to support Zephyr SPI driver for RZ/T2M Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]>
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‎drivers/rz/CMakeLists.txt‎

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@@ -77,6 +77,9 @@ zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_GPT
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_CANFD
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fsp/src/${SOC_SERIES_PREFIX}/r_canfd/r_canfd.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_SPI
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fsp/src/${SOC_SERIES_PREFIX}/r_spi/r_spi.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_RSPI_SPI
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fsp/src/${SOC_SERIES_PREFIX}/r_rspi/r_rspi.c)
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‎drivers/rz/fsp/inc/instances/rzt/r_spi.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef R_SPI_H
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#define R_SPI_H
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/*******************************************************************************************************************//**
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* @addtogroup SPI
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "r_spi_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/*************************************************************************************************
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* Type defines for the SPI interface API
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*************************************************************************************************/
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/** 3-Wire or 4-Wire mode. */
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typedef enum e_spi_ssl_mode
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{
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SPI_SSL_MODE_SPI, ///< SPI operation (4-wire method)
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SPI_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method)
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} spi_ssl_mode_t;
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/** Transmit Only (Half Duplex), or Full Duplex. */
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typedef enum e_spi_communication
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{
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SPI_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication
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SPI_COMMUNICATION_TRANSMIT_ONLY ///< Transit only serial communication
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} spi_communication_t;
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/** Slave Select Polarity. */
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typedef enum e_spi_sslp
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{
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SPI_SSLP_LOW, ///< SSLP signal polarity active low
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SPI_SSLP_HIGH ///< SSLP signal polarity active high
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} spi_ssl_polarity_t;
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/** The Slave Select Line */
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typedef enum e_spi_ssl_select
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{
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SPI_SSL_SELECT_SSL0, ///< Select SSL0
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SPI_SSL_SELECT_SSL1, ///< Select SSL1
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SPI_SSL_SELECT_SSL2, ///< Select SSL2
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SPI_SSL_SELECT_SSL3 ///< Select SSL3
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} spi_ssl_select_t;
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/** MOSI Idle Behavior. */
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typedef enum e_spi_mosi_idle_value_fixing
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{
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SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit
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SPI_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling
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SPI_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling
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} spi_mosi_idle_value_fixing_t;
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/** Parity Mode */
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typedef enum e_spi_parity_mode
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{
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SPI_PARITY_MODE_DISABLE, ///< Disable parity
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SPI_PARITY_MODE_ODD, ///< Select even parity
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SPI_PARITY_MODE_EVEN ///< Select odd parity
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} spi_parity_t;
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/** Byte Swapping Enable/Disable. */
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typedef enum
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{
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SPI_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers
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SPI_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers
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} spi_byte_swap_t;
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/** Delay count for SPI delay settings. */
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typedef enum e_spi_clock_delay_count
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{
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SPI_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK
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SPI_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK
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SPI_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK
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SPI_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK
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SPI_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK
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SPI_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK
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SPI_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK
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SPI_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK
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} spi_delay_count_t;
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/** SPI communication clock source. */
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typedef enum e_spi_clock_source
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{
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SPI_CLOCK_SOURCE_SPI0ASYNCCLK,
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SPI_CLOCK_SOURCE_SPI1ASYNCCLK,
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SPI_CLOCK_SOURCE_SPI2ASYNCCLK,
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SPI_CLOCK_SOURCE_SPI3ASYNCCLK,
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SPI_CLOCK_SOURCE_PCLKM
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} spi_clock_source_t;
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/** SPI master receive clock. */
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typedef enum e_spi_master_receive_clock
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{
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SPI_MASTER_RECEIVE_CLOCK_MRIOCLK, ///< MRIOCLK
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SPI_MASTER_RECEIVE_CLOCK_MRCLK, ///< MRCLK
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} spi_master_receive_clock_t;
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/** SPI max analog delay for MRIOCLK. */
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typedef enum e_spi_mrioclk_analog_delay
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{
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SPI_MRIOCLK_ANALOG_DELAY_NODELAY, ///< No delay
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SPI_MRIOCLK_ANALOG_DELAY_1_1_NS, ///< 1.1 ns
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SPI_MRIOCLK_ANALOG_DELAY_2_2_NS, ///< 2.2 ns
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SPI_MRIOCLK_ANALOG_DELAY_3_3_NS, ///< 3.3 ns
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SPI_MRIOCLK_ANALOG_DELAY_4_4_NS, ///< 4.4 ns
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SPI_MRIOCLK_ANALOG_DELAY_5_5_NS, ///< 5.5 ns
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SPI_MRIOCLK_ANALOG_DELAY_6_6_NS, ///< 6.6 ns
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SPI_MRIOCLK_ANALOG_DELAY_7_7_NS, ///< 7.7 ns
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} spi_mrioclk_analog_delay_t;
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/** SPI digital delay for MRCLK. */
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typedef enum e_spi_mrclk_digital_delay
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{
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_0, ///< 0 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_1, ///< 1 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_2, ///< 2 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_3, ///< 3 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_4, ///< 4 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_5, ///< 5 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_6, ///< 6 PCLKSPIn
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SPI_MRCLK_DIGITAL_DELAY_CLOCK_7, ///< 7 PCLKSPIn
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} spi_mrclk_digital_delay_t;
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/** SPI Clock Divider settings. */
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typedef struct
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{
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uint8_t spbr; ///< SPBR register setting
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uint8_t brdv : 2; ///< BRDV setting in SPCMD0
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} rspck_div_setting_t;
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/** Extended SPI interface configuration */
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typedef struct st_spi_extended_cfg
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{
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spi_ssl_mode_t spi_clksyn; ///< Select spi or clock syn mode operation
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spi_communication_t spi_comm; ///< Select full-duplex or transmit-only communication
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spi_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity
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spi_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3
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spi_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection
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spi_parity_t parity; ///< Select parity and enable/disable parity
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spi_byte_swap_t byte_swap; ///< Select byte swap mode
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spi_clock_source_t clock_source; ///< Communication clock source (PCLKSPI)
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rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider.
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spi_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting
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spi_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting
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spi_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting
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uint8_t transmit_fifo_threshold; ///< Transmit FIFO threshold (0~3)
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uint8_t receive_fifo_threshold; ///< Receive FIFO threshold (0~3)
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uint8_t receive_data_ready_detect_adjustment; ///< Receive data ready detect timing(0~255PCLKSPIn)
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spi_master_receive_clock_t master_receive_clock; ///< SPI master receive clock
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spi_mrioclk_analog_delay_t mrioclk_analog_delay; ///< SPI max analog delay for MRIOCLK
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spi_mrclk_digital_delay_t mrclk_digital_delay; ///< SPI digital delay for MRCLK
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} spi_extended_cfg_t;
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/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */
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typedef struct st_spi_instance_ctrl
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{
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uint32_t open; ///< Indicates whether the open API has been successfully called.
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spi_cfg_t const * p_cfg; ///< Pointer to instance configuration
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R_SPI0_Type * p_regs; ///< Base register for this channel
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void const * p_tx_data; ///< Buffer to transmit
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void * p_rx_data; ///< Buffer to receive
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uint32_t tx_count; ///< Number of Data Frames to transfer (4 to 32 bits)
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uint32_t rx_count; ///< Number of Data Frames to transfer (4 to 32 bits)
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uint32_t count; ///< Number of Data Frames to transfer (4 to 32 bits)
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spi_bit_width_t bit_width; ///< Bits per Data frame (4 to 32 bits)
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/* Pointer to callback and optional working memory */
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void (* p_callback)(spi_callback_args_t *);
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spi_callback_args_t * p_callback_memory;
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/* Pointer to context to be passed into callback function */
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void const * p_context;
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} spi_instance_ctrl_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const spi_api_t g_spi_on_spi;
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/** @endcond */
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/***********************************************************************************************************************
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* Public APIs
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**********************************************************************************************************************/
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fsp_err_t R_SPI_Open(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg);
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fsp_err_t R_SPI_Read(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, spi_bit_width_t const bit_width);
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fsp_err_t R_SPI_Write(spi_ctrl_t * const p_ctrl,
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void const * p_src,
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uint32_t const length,
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spi_bit_width_t const bit_width);
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fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const p_ctrl,
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void const * p_src,
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void * p_dest,
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uint32_t const length,
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spi_bit_width_t const bit_width);
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fsp_err_t R_SPI_Close(spi_ctrl_t * const p_ctrl);
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fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, spi_clock_source_t clock_source, rspck_div_setting_t * spck_div);
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fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_ctrl,
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void ( * p_callback)(spi_callback_args_t *),
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void const * const p_context,
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spi_callback_args_t * const p_callback_memory);
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/*******************************************************************************************************************//**
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* @} (end ingroup SPI)
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**********************************************************************************************************************/
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/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif

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