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| 1 | +From ded064fd2a2f15af197a643db7f77847f4e40857 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Andrew Cooper < [email protected]> |
| 3 | +Date: Tue, 17 Nov 2015 18:11:18 +0000 |
| 4 | +Subject: [PATCH 10/39] tools/libxc: Use public/featureset.h for cpuid policy |
| 5 | + generation |
| 6 | + |
| 7 | +Rather than having a different local copy of some of the feature |
| 8 | +definitions. |
| 9 | + |
| 10 | +Signed-off-by: Andrew Cooper < [email protected]> |
| 11 | +diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h |
| 12 | +deleted file mode 100644 |
| 13 | +index c3ddc80..0000000 |
| 14 | +--- a/tools/libxc/xc_cpufeature.h |
| 15 | ++++ /dev/null |
| 16 | +@@ -1,145 +0,0 @@ |
| 17 | +-/* |
| 18 | +- * This library is free software; you can redistribute it and/or |
| 19 | +- * modify it under the terms of the GNU Lesser General Public |
| 20 | +- * License as published by the Free Software Foundation; |
| 21 | +- * version 2.1 of the License. |
| 22 | +- * |
| 23 | +- * This library is distributed in the hope that it will be useful, |
| 24 | +- * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 25 | +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 26 | +- * Lesser General Public License for more details. |
| 27 | +- * |
| 28 | +- * You should have received a copy of the GNU Lesser General Public |
| 29 | +- * License along with this library; If not, see <http://www.gnu.org/licenses/>. |
| 30 | +- */ |
| 31 | +- |
| 32 | +-#ifndef __LIBXC_CPUFEATURE_H |
| 33 | +-#define __LIBXC_CPUFEATURE_H |
| 34 | +- |
| 35 | +-/* Intel-defined CPU features, CPUID level 0x00000001 (edx) */ |
| 36 | +-#define X86_FEATURE_FPU 0 /* Onboard FPU */ |
| 37 | +-#define X86_FEATURE_VME 1 /* Virtual Mode Extensions */ |
| 38 | +-#define X86_FEATURE_DE 2 /* Debugging Extensions */ |
| 39 | +-#define X86_FEATURE_PSE 3 /* Page Size Extensions */ |
| 40 | +-#define X86_FEATURE_TSC 4 /* Time Stamp Counter */ |
| 41 | +-#define X86_FEATURE_MSR 5 /* Model-Specific Registers, RDMSR, WRMSR */ |
| 42 | +-#define X86_FEATURE_PAE 6 /* Physical Address Extensions */ |
| 43 | +-#define X86_FEATURE_MCE 7 /* Machine Check Architecture */ |
| 44 | +-#define X86_FEATURE_CX8 8 /* CMPXCHG8 instruction */ |
| 45 | +-#define X86_FEATURE_APIC 9 /* Onboard APIC */ |
| 46 | +-#define X86_FEATURE_SEP 11 /* SYSENTER/SYSEXIT */ |
| 47 | +-#define X86_FEATURE_MTRR 12 /* Memory Type Range Registers */ |
| 48 | +-#define X86_FEATURE_PGE 13 /* Page Global Enable */ |
| 49 | +-#define X86_FEATURE_MCA 14 /* Machine Check Architecture */ |
| 50 | +-#define X86_FEATURE_CMOV 15 /* CMOV instruction */ |
| 51 | +-#define X86_FEATURE_PAT 16 /* Page Attribute Table */ |
| 52 | +-#define X86_FEATURE_PSE36 17 /* 36-bit PSEs */ |
| 53 | +-#define X86_FEATURE_PN 18 /* Processor serial number */ |
| 54 | +-#define X86_FEATURE_CLFLSH 19 /* Supports the CLFLUSH instruction */ |
| 55 | +-#define X86_FEATURE_DS 21 /* Debug Store */ |
| 56 | +-#define X86_FEATURE_ACPI 22 /* ACPI via MSR */ |
| 57 | +-#define X86_FEATURE_MMX 23 /* Multimedia Extensions */ |
| 58 | +-#define X86_FEATURE_FXSR 24 /* FXSAVE and FXRSTOR instructions */ |
| 59 | +-#define X86_FEATURE_XMM 25 /* Streaming SIMD Extensions */ |
| 60 | +-#define X86_FEATURE_XMM2 26 /* Streaming SIMD Extensions-2 */ |
| 61 | +-#define X86_FEATURE_SELFSNOOP 27 /* CPU self snoop */ |
| 62 | +-#define X86_FEATURE_HT 28 /* Hyper-Threading */ |
| 63 | +-#define X86_FEATURE_ACC 29 /* Automatic clock control */ |
| 64 | +-#define X86_FEATURE_IA64 30 /* IA-64 processor */ |
| 65 | +-#define X86_FEATURE_PBE 31 /* Pending Break Enable */ |
| 66 | +- |
| 67 | +-/* AMD-defined CPU features, CPUID level 0x80000001 */ |
| 68 | +-/* Don't duplicate feature flags which are redundant with Intel! */ |
| 69 | +-#define X86_FEATURE_SYSCALL 11 /* SYSCALL/SYSRET */ |
| 70 | +-#define X86_FEATURE_MP 19 /* MP Capable. */ |
| 71 | +-#define X86_FEATURE_NX 20 /* Execute Disable */ |
| 72 | +-#define X86_FEATURE_MMXEXT 22 /* AMD MMX extensions */ |
| 73 | +-#define X86_FEATURE_FFXSR 25 /* FFXSR instruction optimizations */ |
| 74 | +-#define X86_FEATURE_PAGE1GB 26 /* 1Gb large page support */ |
| 75 | +-#define X86_FEATURE_RDTSCP 27 /* RDTSCP */ |
| 76 | +-#define X86_FEATURE_LM 29 /* Long Mode (x86-64) */ |
| 77 | +-#define X86_FEATURE_3DNOWEXT 30 /* AMD 3DNow! extensions */ |
| 78 | +-#define X86_FEATURE_3DNOW 31 /* 3DNow! */ |
| 79 | +- |
| 80 | +-/* Intel-defined CPU features, CPUID level 0x00000001 (ecx) */ |
| 81 | +-#define X86_FEATURE_XMM3 0 /* Streaming SIMD Extensions-3 */ |
| 82 | +-#define X86_FEATURE_PCLMULQDQ 1 /* Carry-less multiplication */ |
| 83 | +-#define X86_FEATURE_DTES64 2 /* 64-bit Debug Store */ |
| 84 | +-#define X86_FEATURE_MWAIT 3 /* Monitor/Mwait support */ |
| 85 | +-#define X86_FEATURE_DSCPL 4 /* CPL Qualified Debug Store */ |
| 86 | +-#define X86_FEATURE_VMXE 5 /* Virtual Machine Extensions */ |
| 87 | +-#define X86_FEATURE_SMXE 6 /* Safer Mode Extensions */ |
| 88 | +-#define X86_FEATURE_EST 7 /* Enhanced SpeedStep */ |
| 89 | +-#define X86_FEATURE_TM2 8 /* Thermal Monitor 2 */ |
| 90 | +-#define X86_FEATURE_SSSE3 9 /* Supplemental Streaming SIMD Exts-3 */ |
| 91 | +-#define X86_FEATURE_CID 10 /* Context ID */ |
| 92 | +-#define X86_FEATURE_FMA 12 /* Fused Multiply Add */ |
| 93 | +-#define X86_FEATURE_CX16 13 /* CMPXCHG16B */ |
| 94 | +-#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */ |
| 95 | +-#define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */ |
| 96 | +-#define X86_FEATURE_PCID 17 /* Process Context ID */ |
| 97 | +-#define X86_FEATURE_DCA 18 /* Direct Cache Access */ |
| 98 | +-#define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */ |
| 99 | +-#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */ |
| 100 | +-#define X86_FEATURE_X2APIC 21 /* x2APIC */ |
| 101 | +-#define X86_FEATURE_MOVBE 22 /* movbe instruction */ |
| 102 | +-#define X86_FEATURE_POPCNT 23 /* POPCNT instruction */ |
| 103 | +-#define X86_FEATURE_TSC_DEADLINE 24 /* "tdt" TSC Deadline Timer */ |
| 104 | +-#define X86_FEATURE_AES 25 /* AES acceleration instructions */ |
| 105 | +-#define X86_FEATURE_XSAVE 26 /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
| 106 | +-#define X86_FEATURE_AVX 28 /* Advanced Vector Extensions */ |
| 107 | +-#define X86_FEATURE_F16C 29 /* Half-precision convert instruction */ |
| 108 | +-#define X86_FEATURE_RDRAND 30 /* Digital Random Number Generator */ |
| 109 | +-#define X86_FEATURE_HYPERVISOR 31 /* Running under some hypervisor */ |
| 110 | +- |
| 111 | +-/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001 */ |
| 112 | +-#define X86_FEATURE_XSTORE 2 /* on-CPU RNG present (xstore insn) */ |
| 113 | +-#define X86_FEATURE_XSTORE_EN 3 /* on-CPU RNG enabled */ |
| 114 | +-#define X86_FEATURE_XCRYPT 6 /* on-CPU crypto (xcrypt insn) */ |
| 115 | +-#define X86_FEATURE_XCRYPT_EN 7 /* on-CPU crypto enabled */ |
| 116 | +-#define X86_FEATURE_ACE2 8 /* Advanced Cryptography Engine v2 */ |
| 117 | +-#define X86_FEATURE_ACE2_EN 9 /* ACE v2 enabled */ |
| 118 | +-#define X86_FEATURE_PHE 10 /* PadLock Hash Engine */ |
| 119 | +-#define X86_FEATURE_PHE_EN 11 /* PHE enabled */ |
| 120 | +-#define X86_FEATURE_PMM 12 /* PadLock Montgomery Multiplier */ |
| 121 | +-#define X86_FEATURE_PMM_EN 13 /* PMM enabled */ |
| 122 | +- |
| 123 | +-/* More extended AMD flags: CPUID level 0x80000001, ecx */ |
| 124 | +-#define X86_FEATURE_LAHF_LM 0 /* LAHF/SAHF in long mode */ |
| 125 | +-#define X86_FEATURE_CMP_LEGACY 1 /* If yes HyperThreading not valid */ |
| 126 | +-#define X86_FEATURE_SVM 2 /* Secure virtual machine */ |
| 127 | +-#define X86_FEATURE_EXTAPIC 3 /* Extended APIC space */ |
| 128 | +-#define X86_FEATURE_CR8_LEGACY 4 /* CR8 in 32-bit mode */ |
| 129 | +-#define X86_FEATURE_ABM 5 /* Advanced bit manipulation */ |
| 130 | +-#define X86_FEATURE_SSE4A 6 /* SSE-4A */ |
| 131 | +-#define X86_FEATURE_MISALIGNSSE 7 /* Misaligned SSE mode */ |
| 132 | +-#define X86_FEATURE_3DNOWPREFETCH 8 /* 3DNow prefetch instructions */ |
| 133 | +-#define X86_FEATURE_OSVW 9 /* OS Visible Workaround */ |
| 134 | +-#define X86_FEATURE_IBS 10 /* Instruction Based Sampling */ |
| 135 | +-#define X86_FEATURE_XOP 11 /* extended AVX instructions */ |
| 136 | +-#define X86_FEATURE_SKINIT 12 /* SKINIT/STGI instructions */ |
| 137 | +-#define X86_FEATURE_WDT 13 /* Watchdog timer */ |
| 138 | +-#define X86_FEATURE_LWP 15 /* Light Weight Profiling */ |
| 139 | +-#define X86_FEATURE_FMA4 16 /* 4 operands MAC instructions */ |
| 140 | +-#define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */ |
| 141 | +-#define X86_FEATURE_TBM 21 /* trailing bit manipulations */ |
| 142 | +-#define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */ |
| 143 | +-#define X86_FEATURE_DBEXT 26 /* data breakpoint extension */ |
| 144 | +- |
| 145 | +-/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */ |
| 146 | +-#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */ |
| 147 | +-#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */ |
| 148 | +-#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */ |
| 149 | +-#define X86_FEATURE_HLE 4 /* Hardware Lock Elision */ |
| 150 | +-#define X86_FEATURE_AVX2 5 /* AVX2 instructions */ |
| 151 | +-#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */ |
| 152 | +-#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */ |
| 153 | +-#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */ |
| 154 | +-#define X86_FEATURE_INVPCID 10 /* Invalidate Process Context ID */ |
| 155 | +-#define X86_FEATURE_RTM 11 /* Restricted Transactional Memory */ |
| 156 | +-#define X86_FEATURE_RDSEED 18 /* RDSEED instruction */ |
| 157 | +-#define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ |
| 158 | +-#define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ |
| 159 | +- |
| 160 | +- |
| 161 | +-#endif /* __LIBXC_CPUFEATURE_H */ |
| 162 | +diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c |
| 163 | +index 031c848..0a806cb 100644 |
| 164 | +--- a/tools/libxc/xc_cpuid_x86.c |
| 165 | ++++ b/tools/libxc/xc_cpuid_x86.c |
| 166 | +@@ -22,12 +22,12 @@ |
| 167 | + #include <stdlib.h> |
| 168 | + #include <stdbool.h> |
| 169 | + #include "xc_private.h" |
| 170 | +-#include "xc_cpufeature.h" |
| 171 | ++#include <xen/arch-x86/featureset.h> |
| 172 | + #include <xen/hvm/params.h> |
| 173 | + |
| 174 | +-#define bitmaskof(idx) (1u << (idx)) |
| 175 | +-#define clear_bit(idx, dst) ((dst) &= ~(1u << (idx))) |
| 176 | +-#define set_bit(idx, dst) ((dst) |= (1u << (idx))) |
| 177 | ++#define bitmaskof(idx) (1u << ((idx) & 31)) |
| 178 | ++#define clear_bit(idx, dst) ((dst) &= ~bitmaskof(idx)) |
| 179 | ++#define set_bit(idx, dst) ((dst) |= bitmaskof(idx)) |
| 180 | + |
| 181 | + #define DEF_MAX_BASE 0x0000000du |
| 182 | + #define DEF_MAX_INTELEXT 0x80000008u |
| 183 | +diff --git a/xen/include/public/arch-x86/featureset.h b/xen/include/public/arch-x86/featureset.h |
| 184 | +index 9a01d10..97e5c61 100644 |
| 185 | +--- a/xen/include/public/arch-x86/featureset.h |
| 186 | ++++ b/xen/include/public/arch-x86/featureset.h |
| 187 | +@@ -163,6 +163,7 @@ |
| 188 | + |
| 189 | + /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ |
| 190 | + #define X86_FEATURE_FSGSBASE ( 5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ |
| 191 | ++#define X86_FEATURE_TSC_ADJUST ( 5*32+ 1) /* TSC_ADJUST MSR available */ |
| 192 | + #define X86_FEATURE_BMI1 ( 5*32+ 3) /* 1st bit manipulation extensions */ |
| 193 | + #define X86_FEATURE_HLE ( 5*32+ 4) /* Hardware Lock Elision */ |
| 194 | + #define X86_FEATURE_AVX2 ( 5*32+ 5) /* AVX2 instructions */ |
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