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lines changed Original file line number Diff line number Diff line change 33
44add_subdirectory (${ZEPHYR_CURRENT_MODULE_DIR} cmsis)
55
6- if (CONFIG_CPU_CORTEX_M OR CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
6+ if (CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
77 zephyr_include_directories(.)
88endif ()
Original file line number Diff line number Diff line change @@ -8,7 +8,6 @@ config HAS_CMSIS_CORE
88 bool
99 select HAS_CMSIS_CORE_A if CPU_AARCH32_CORTEX_A
1010 select HAS_CMSIS_CORE_R if CPU_AARCH32_CORTEX_R
11- select HAS_CMSIS_CORE_M if CPU_CORTEX_M
1211
1312if HAS_CMSIS_CORE
1413
@@ -18,19 +17,4 @@ config HAS_CMSIS_CORE_A
1817config HAS_CMSIS_CORE_R
1918 bool
2019
21- config HAS_CMSIS_CORE_M
22- bool
23-
24- config CMSIS_M_CHECK_DEVICE_DEFINES
25- bool "Check device defines"
26- default n
27- depends on HAS_CMSIS_CORE_M
28- help
29- This options enables the validation of CMSIS configuration flags.
30-
31- config CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK
32- bool
33- help
34- Enable this option if CMSIS SystemCoreClock symbols is available.
35-
3620endif
Original file line number Diff line number Diff line change 66#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_H_
77#define ZEPHYR_MODULES_CMSIS_CMSIS_H_
88
9- #if defined(CONFIG_CPU_CORTEX_M )
10- #include "cmsis_core_m.h"
11- #elif defined(CONFIG_CPU_AARCH32_CORTEX_A ) || defined(CONFIG_CPU_AARCH32_CORTEX_R )
9+ #if defined(CONFIG_CPU_AARCH32_CORTEX_A ) || defined(CONFIG_CPU_AARCH32_CORTEX_R )
1210#include "cmsis_core_a_r.h"
1311#endif
1412
Original file line number Diff line number Diff line change 1+ # Copyright (c) 2023 Nordic Semiconductor ASA
2+ # Copyright 2025 Arm Limited and/or its affiliates <[email protected] > 3+ # SPDX-License-Identifier: Apache-2.0
4+
5+ add_subdirectory (${ZEPHYR_CURRENT_MODULE_DIR} cmsis_6)
6+
7+ if (CONFIG_CPU_CORTEX_M)
8+ zephyr_include_directories(.)
9+ endif ()
Original file line number Diff line number Diff line change 1+ # Copyright (c) 2016 Intel Corporation
2+ # Copyright 2025 Arm Limited and/or its affiliates <
[email protected] >
3+ # SPDX-License-Identifier: Apache-2.0
4+
5+ config ZEPHYR_CMSIS_6_MODULE
6+ bool
7+
8+ config HAS_CMSIS_CORE
9+ bool
10+ select HAS_CMSIS_CORE_M if CPU_CORTEX_M
11+
12+ if HAS_CMSIS_CORE
13+
14+ config HAS_CMSIS_CORE_M
15+ bool
16+
17+ config CMSIS_M_CHECK_DEVICE_DEFINES
18+ bool "Check device defines"
19+ depends on HAS_CMSIS_CORE_M
20+ help
21+ This options enables the validation of CMSIS configuration flags.
22+
23+ config CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK
24+ bool
25+ help
26+ Enable this option if CMSIS SystemCoreClock symbols is available.
27+
28+ endif
Original file line number Diff line number Diff line change 1+ /*
2+ * Copyright (c) 2023 Nordic Semiconductor ASA
3+ * Copyright 2025 Arm Limited and/or its affiliates <[email protected] > 4+ * SPDX-License-Identifier: Apache-2.0
5+ */
6+
7+ #ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_
8+ #define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_
9+
10+ #if defined(CONFIG_CPU_CORTEX_M )
11+ #include "cmsis_core_m.h"
12+ #endif
13+
14+ #endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_ */
Original file line number Diff line number Diff line change 11/*
22 * Copyright (c) 2017 Nordic Semiconductor ASA
3- * Copyright (c) 2023 Arm Limited
3+ * Copyright 2023,2025 Arm Limited and/or its affiliates <[email protected] > 44 *
55 * SPDX-License-Identifier: Apache-2.0
66 */
1212 * This header contains the interface to the ARM CMSIS Core headers.
1313 */
1414
15- #ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
16- #define ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
15+ #ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_
16+ #define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_
1717
1818#if defined(CONFIG_CMSIS_M_CHECK_DEVICE_DEFINES ) && CONFIG_CMSIS_M_CHECK_DEVICE_DEFINES == 1U
1919#define __CHECK_DEVICE_DEFINES 1U
6868#error "__SAUREGION_PRESENT and CONFIG_CPU_HAS_ARM_SAU are not set to the same value"
6969#endif
7070
71- #endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ */
71+ #endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_ */
Original file line number Diff line number Diff line change 11/*
22 * Copyright (c) 2017 Nordic Semiconductor ASA
3- * Copyright (c) 2023 Arm Limited
3+ * Copyright 2023,2025 Arm Limited and/or its affiliates <[email protected] > 44 *
55 * SPDX-License-Identifier: Apache-2.0
66 */
1313 * ARM CMSIS Core headers.
1414 */
1515
16- #ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
17- #define ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
16+ #ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_
17+ #define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_
1818
1919#include <zephyr/arch/arm/cortex_m/nvic.h>
2020
@@ -143,4 +143,4 @@ typedef enum {
143143#error "Unknown Cortex-M device"
144144#endif
145145
146- #endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ */
146+ #endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_ */
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