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soheilshahrouzsoheilshahrouz
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use std:string for storing pin names in t_pin_to_pin_annotations
1 parent 4f10eb2 commit 34bb767

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14 files changed

+148
-169
lines changed

14 files changed

+148
-169
lines changed

‎libs/libarchfpga/src/arch_check.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -163,11 +163,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
163163
if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) {
164164
//Check that any combinational delays specified match the 'combinational_sinks_ports' in the model
165165

166-
if (annotation.clock) {
166+
if (!annotation.clock.empty()) {
167167
//Sequential annotation, check that the clock on the specified port matches the model
168168

169-
//Annotations always put the pin in the input_pins field
170-
VTR_ASSERT(annotation.input_pins);
169+
// Annotations always put the pin in the input_pins field
170+
VTR_ASSERT(!annotation.input_pins.empty());
171171
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
172172
InstPort annot_port(input_pin);
173173
for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) {
@@ -207,15 +207,15 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
207207
}
208208
}
209209

210-
} else if (annotation.input_pins && annotation.output_pins) {
211-
//Combinational annotation
212-
VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
210+
} else if (!annotation.input_pins.empty() && !annotation.output_pins.empty()) {
211+
// Combinational annotation
212+
VTR_ASSERT_MSG(annotation.clock.empty(), "Combinational annotations should have no clock");
213213
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
214214
InstPort annot_in(input_pin);
215215
for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
216216
InstPort annot_out(output_pin);
217217

218-
//Find the input model port
218+
// Find the input model port
219219
const t_model_ports* model_port = nullptr;
220220
for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) {
221221
if (port->name == annot_in.port_name()) {
@@ -230,7 +230,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
230230
annot_in.port_name().c_str(), annot_in.instance_name().c_str());
231231
}
232232

233-
//Check that the output port is listed in the model's combinational sinks
233+
// Check that the output port is listed in the model's combinational sinks
234234
auto b = model_port->combinational_sink_ports.begin();
235235
auto e = model_port->combinational_sink_ports.end();
236236
auto iter = std::find(b, e, annot_out.port_name());

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 18 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -320,11 +320,6 @@ static void free_pb_type(t_pb_type* pb_type) {
320320
vtr::free(pb_type->modes[i].interconnect[j].output_string);
321321
vtr::free(pb_type->modes[i].interconnect[j].name);
322322

323-
for (t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) {
324-
vtr::free(annotation.clock);
325-
vtr::free(annotation.input_pins);
326-
vtr::free(annotation.output_pins);
327-
}
328323
pb_type->modes[i].interconnect[j].annotations.clear();
329324
delete pb_type->modes[i].interconnect[j].interconnect_power;
330325
}
@@ -333,12 +328,6 @@ static void free_pb_type(t_pb_type* pb_type) {
333328
}
334329

335330
delete[] pb_type->modes;
336-
337-
for (t_pin_to_pin_annotation& annotation : pb_type->annotations) {
338-
vtr::free(annotation.input_pins);
339-
vtr::free(annotation.output_pins);
340-
vtr::free(annotation.clock);
341-
}
342331
pb_type->annotations.clear();
343332

344333
delete pb_type->pb_type_power;
@@ -439,13 +428,11 @@ std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical
439428
}
440429

441430
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
442-
char* new_name,
431+
std::string_view new_name,
443432
t_pb_type* copy) {
444-
char* dot;
445-
446433
VTR_ASSERT(pb_type->blif_model != nullptr);
447434

448-
copy->name = vtr::strdup(new_name);
435+
copy->name = vtr::strdup(new_name.data());
449436
copy->blif_model = vtr::strdup(pb_type->blif_model);
450437
copy->class_type = pb_type->class_type;
451438
copy->depth = pb_type->depth;
@@ -482,8 +469,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
482469
if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) {
483470
copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO;
484471
copy->ports[i].port_power->buffer_type = POWER_BUFFER_TYPE_AUTO;
485-
} else if (copy->pb_type_power->estimation_method
486-
== POWER_METHOD_SPECIFY_SIZES) {
472+
} else if (copy->pb_type_power->estimation_method == POWER_METHOD_SPECIFY_SIZES) {
487473
copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_IGNORED;
488474
copy->ports[i].port_power->buffer_type = POWER_BUFFER_TYPE_NONE;
489475
}
@@ -492,20 +478,18 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
492478
size_t num_annotations = pb_type->annotations.size();
493479
copy->annotations.resize(num_annotations);
494480
for (size_t i = 0; i < num_annotations; i++) {
495-
copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock);
496-
dot = strstr(pb_type->annotations[i].input_pins, ".");
497-
copy->annotations[i].input_pins = (char*)vtr::malloc(sizeof(char) * (strlen(new_name) + strlen(dot) + 1));
498-
copy->annotations[i].input_pins[0] = '\0';
499-
strcat(copy->annotations[i].input_pins, new_name);
500-
strcat(copy->annotations[i].input_pins, dot);
501-
if (pb_type->annotations[i].output_pins != nullptr) {
502-
dot = strstr(pb_type->annotations[i].output_pins, ".");
503-
copy->annotations[i].output_pins = (char*)vtr::malloc(sizeof(char) * (strlen(new_name) + strlen(dot) + 1));
504-
copy->annotations[i].output_pins[0] = '\0';
505-
strcat(copy->annotations[i].output_pins, new_name);
506-
strcat(copy->annotations[i].output_pins, dot);
481+
copy->annotations[i].clock = pb_type->annotations[i].clock;
482+
483+
auto dot_pos = pb_type->annotations[i].input_pins.find('.');
484+
VTR_ASSERT_MSG(dot_pos != std::string::npos, "Expected '.' in input_pins");
485+
copy->annotations[i].input_pins = std::string(new_name) + pb_type->annotations[i].input_pins.substr(dot_pos);
486+
487+
if (!pb_type->annotations[i].output_pins.empty()) {
488+
dot_pos = pb_type->annotations[i].output_pins.find('.');
489+
VTR_ASSERT_MSG(dot_pos != std::string::npos, "Expected '.' in output_pins");
490+
copy->annotations[i].output_pins = std::string(new_name) + pb_type->annotations[i].output_pins.substr(dot_pos);
507491
} else {
508-
copy->annotations[i].output_pins = nullptr;
492+
copy->annotations[i].output_pins.clear();
509493
}
510494
copy->annotations[i].line_num = pb_type->annotations[i].line_num;
511495
copy->annotations[i].format = pb_type->annotations[i].format;
@@ -572,9 +556,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
572556
size_t num_annotations = lut_pb_type->annotations.size();
573557
lut_pb_type->modes[0].interconnect[0].annotations.resize(num_annotations);
574558
for (size_t i = 0; i < num_annotations; i++) {
575-
lut_pb_type->modes[0].interconnect[0].annotations[i].clock = vtr::strdup(lut_pb_type->annotations[i].clock);
576-
lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = vtr::strdup(lut_pb_type->annotations[i].input_pins);
577-
lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins = vtr::strdup(lut_pb_type->annotations[i].output_pins);
559+
lut_pb_type->modes[0].interconnect[0].annotations[i].clock = lut_pb_type->annotations[i].clock;
560+
lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = lut_pb_type->annotations[i].input_pins;
561+
lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins =lut_pb_type->annotations[i].output_pins;
578562
lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num;
579563
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
580564
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
@@ -592,12 +576,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
592576
lut_pb_type->modes[1].pb_type_children = new t_pb_type[1];
593577
alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name,
594578
lut_pb_type->modes[1].pb_type_children);
595-
/* moved annotations to child so delete old annotations */
596-
for (size_t i = 0; i < num_annotations; i++) {
597-
vtr::free(lut_pb_type->annotations[i].input_pins);
598-
vtr::free(lut_pb_type->annotations[i].output_pins);
599-
vtr::free(lut_pb_type->annotations[i].clock);
600-
}
601579
lut_pb_type->annotations.clear();
602580
lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1;
603581
lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1];
@@ -962,8 +940,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
962940

963941
for (i_port = 0; i_port < parent_pb_type->num_ports; i_port++) {
964942
if (parent_pb_type->ports[i_port].is_clock) {
965-
if (strcmp(parent_pb_type->ports[i_port].name, annotation->clock)
966-
== 0) {
943+
if (parent_pb_type->ports[i_port].name == annotation->clock) {
967944
clock_valid = true;
968945
break;
969946
}

‎libs/libarchfpga/src/arch_util.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ t_logical_block_type get_empty_logical_type(const char* name = EMPTY_BLOCK_NAME)
6969
std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type);
7070

7171
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
72-
char* new_name,
72+
std::string_view new_name,
7373
t_pb_type* copy);
7474

7575
void ProcessLutClass(t_pb_type* lut_pb_type);

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -401,8 +401,8 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
401401
pb_type->modes[i].interconnect[j].output_string);
402402
for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) {
403403
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(),
404-
annotation.input_pins,
405-
annotation.output_pins,
404+
annotation.input_pins.c_str(),
405+
annotation.output_pins.c_str(),
406406
annotation.format,
407407
annotation.annotation_entries[0].second.c_str());
408408
}
@@ -428,9 +428,9 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
428428
&& pb_type_model_name != LogicalModels::MODEL_OUTPUT) {
429429
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
430430
fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(),
431-
annotation.clock,
432-
annotation.input_pins,
433-
annotation.output_pins,
431+
annotation.clock.c_str(),
432+
annotation.input_pins.c_str(),
433+
annotation.output_pins.c_str(),
434434
annotation.format,
435435
annotation.annotation_entries[0].second.c_str());
436436
}

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,18 +1076,13 @@ struct t_pin_to_pin_annotation {
10761076
e_pin_to_pin_annotation_type type;
10771077
e_pin_to_pin_annotation_format format;
10781078

1079-
char* input_pins;
1080-
char* output_pins;
1081-
char* clock;
1079+
std::string input_pins;
1080+
std::string output_pins;
1081+
std::string clock;
10821082

10831083
int line_num; /* used to report what line number this annotation is found in architecture file */
10841084

10851085
t_pin_to_pin_annotation() noexcept {
1086-
annotation_entries = std::vector<std::pair<int, std::string>>();
1087-
input_pins = nullptr;
1088-
output_pins = nullptr;
1089-
clock = nullptr;
1090-
10911086
line_num = 0;
10921087
type = (e_pin_to_pin_annotation_type)0;
10931088
format = (e_pin_to_pin_annotation_format)0;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -242,28 +242,28 @@ static t_port get_generic_port(t_arch* arch,
242242
}
243243

244244
/** @brief Returns true if a given port name exists in the given complex block */
245-
static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
245+
static bool block_port_exists(t_pb_type* pb_type, std::string_view port_name) {
246246
for (int iport = 0; iport < pb_type->num_ports; iport++) {
247247
const t_port port = pb_type->ports[iport];
248248

249-
if (std::string(port.name) == port_name)
249+
if (port.name == port_name)
250250
return true;
251251
}
252252

253253
return false;
254254
}
255255

256-
/** @brief Returns a pack pattern given it's name, input and output strings */
257-
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
256+
/** @brief Returns a pack pattern given its name, input and output strings */
257+
static t_pin_to_pin_annotation get_pack_pattern(std::string_view pp_name, std::string_view input, std::string_view output) {
258258
t_pin_to_pin_annotation pp;
259259

260260
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
261261
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
262-
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
263-
pp.input_pins = vtr::strdup(input.c_str());
264-
pp.output_pins = vtr::strdup(output.c_str());
262+
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name.data()});
263+
pp.input_pins = input;
264+
pp.output_pins = output;
265265

266-
pp.clock = nullptr;
266+
pp.clock.clear();
267267

268268
return pp;
269269
}

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