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[RISCV] Add more instructions for the short forward branch optimization. (llvm#66789)
This adds the shifts and the immediate forms of the instructions that were already supported. There are still more instructions that can be predicated, but this is the rest of what we had in our downstream.
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‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -126,6 +126,23 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
126126
case RISCV::PseudoCCXOR:
127127
case RISCV::PseudoCCADDW:
128128
case RISCV::PseudoCCSUBW:
129+
case RISCV::PseudoCCSLL:
130+
case RISCV::PseudoCCSRL:
131+
case RISCV::PseudoCCSRA:
132+
case RISCV::PseudoCCADDI:
133+
case RISCV::PseudoCCSLLI:
134+
case RISCV::PseudoCCSRLI:
135+
case RISCV::PseudoCCSRAI:
136+
case RISCV::PseudoCCANDI:
137+
case RISCV::PseudoCCORI:
138+
case RISCV::PseudoCCXORI:
139+
case RISCV::PseudoCCSLLW:
140+
case RISCV::PseudoCCSRLW:
141+
case RISCV::PseudoCCSRAW:
142+
case RISCV::PseudoCCADDIW:
143+
case RISCV::PseudoCCSLLIW:
144+
case RISCV::PseudoCCSRLIW:
145+
case RISCV::PseudoCCSRAIW:
129146
return expandCCOp(MBB, MBBI, NextMBBI);
130147
case RISCV::PseudoVSETVLI:
131148
case RISCV::PseudoVSETVLIX0:
@@ -197,11 +214,28 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
197214
llvm_unreachable("Unexpected opcode!");
198215
case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
199216
case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
217+
case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
218+
case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
219+
case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
200220
case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
201221
case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
202222
case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
223+
case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
224+
case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
225+
case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
226+
case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
227+
case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
228+
case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
229+
case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
203230
case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
204231
case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
232+
case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
233+
case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
234+
case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
235+
case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
236+
case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
237+
case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
238+
case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
205239
}
206240
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
207241
.add(MI.getOperand(5))

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1209,12 +1209,31 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
12091209
switch (Opcode) {
12101210
case RISCV::ADD: return RISCV::PseudoCCADD; break;
12111211
case RISCV::SUB: return RISCV::PseudoCCSUB; break;
1212+
case RISCV::SLL: return RISCV::PseudoCCSLL; break;
1213+
case RISCV::SRL: return RISCV::PseudoCCSRL; break;
1214+
case RISCV::SRA: return RISCV::PseudoCCSRA; break;
12121215
case RISCV::AND: return RISCV::PseudoCCAND; break;
12131216
case RISCV::OR: return RISCV::PseudoCCOR; break;
12141217
case RISCV::XOR: return RISCV::PseudoCCXOR; break;
12151218

1219+
case RISCV::ADDI: return RISCV::PseudoCCADDI; break;
1220+
case RISCV::SLLI: return RISCV::PseudoCCSLLI; break;
1221+
case RISCV::SRLI: return RISCV::PseudoCCSRLI; break;
1222+
case RISCV::SRAI: return RISCV::PseudoCCSRAI; break;
1223+
case RISCV::ANDI: return RISCV::PseudoCCANDI; break;
1224+
case RISCV::ORI: return RISCV::PseudoCCORI; break;
1225+
case RISCV::XORI: return RISCV::PseudoCCXORI; break;
1226+
12161227
case RISCV::ADDW: return RISCV::PseudoCCADDW; break;
12171228
case RISCV::SUBW: return RISCV::PseudoCCSUBW; break;
1229+
case RISCV::SLLW: return RISCV::PseudoCCSLLW; break;
1230+
case RISCV::SRLW: return RISCV::PseudoCCSRLW; break;
1231+
case RISCV::SRAW: return RISCV::PseudoCCSRAW; break;
1232+
1233+
case RISCV::ADDIW: return RISCV::PseudoCCADDIW; break;
1234+
case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
1235+
case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
1236+
case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
12181237
}
12191238

12201239
return RISCV::INSTRUCTION_LIST_END;
@@ -1235,6 +1254,10 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
12351254
// Check if MI can be predicated and folded into the CCMOV.
12361255
if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
12371256
return nullptr;
1257+
// Don't predicate li idiom.
1258+
if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
1259+
MI->getOperand(1).getReg() == RISCV::X0)
1260+
return nullptr;
12381261
// Check if MI has any other defs or physreg uses.
12391262
for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
12401263
// Reject frame index operands, PEI can't handle the predicated pseudos.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1444,6 +1444,21 @@ def PseudoCCSUB : Pseudo<(outs GPR:$dst),
14441444
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
14451445
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14461446
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1447+
def PseudoCCSLL : Pseudo<(outs GPR:$dst),
1448+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1449+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1450+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1451+
ReadSFBALU, ReadSFBALU]>;
1452+
def PseudoCCSRL : Pseudo<(outs GPR:$dst),
1453+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1454+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1455+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1456+
ReadSFBALU, ReadSFBALU]>;
1457+
def PseudoCCSRA : Pseudo<(outs GPR:$dst),
1458+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1459+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1460+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1461+
ReadSFBALU, ReadSFBALU]>;
14471462
def PseudoCCAND : Pseudo<(outs GPR:$dst),
14481463
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
14491464
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
@@ -1460,6 +1475,42 @@ def PseudoCCXOR : Pseudo<(outs GPR:$dst),
14601475
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14611476
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
14621477

1478+
def PseudoCCADDI : Pseudo<(outs GPR:$dst),
1479+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1480+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1481+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1482+
ReadSFBALU]>;
1483+
def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
1484+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1485+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1486+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1487+
ReadSFBALU]>;
1488+
def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
1489+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1490+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1491+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1492+
ReadSFBALU]>;
1493+
def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
1494+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1495+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1496+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1497+
ReadSFBALU]>;
1498+
def PseudoCCANDI : Pseudo<(outs GPR:$dst),
1499+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1500+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1501+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1502+
ReadSFBALU]>;
1503+
def PseudoCCORI : Pseudo<(outs GPR:$dst),
1504+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1505+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1506+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1507+
ReadSFBALU]>;
1508+
def PseudoCCXORI : Pseudo<(outs GPR:$dst),
1509+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1510+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1511+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1512+
ReadSFBALU]>;
1513+
14631514
// RV64I instructions
14641515
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
14651516
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
@@ -1471,6 +1522,42 @@ def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
14711522
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
14721523
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14731524
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1525+
def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
1526+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1527+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1528+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1529+
ReadSFBALU, ReadSFBALU]>;
1530+
def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
1531+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1532+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1533+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1534+
ReadSFBALU, ReadSFBALU]>;
1535+
def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
1536+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1537+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1538+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1539+
ReadSFBALU, ReadSFBALU]>;
1540+
1541+
def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
1542+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1543+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1544+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1545+
ReadSFBALU]>;
1546+
def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
1547+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1548+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1549+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1550+
ReadSFBALU]>;
1551+
def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
1552+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1553+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1554+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1555+
ReadSFBALU]>;
1556+
def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
1557+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1558+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1559+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1560+
ReadSFBALU]>;
14741561
}
14751562

14761563
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {

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