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amanasifkhalidrzikm
amanasifkhalid
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rzikm
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ARM64-SVE: Add Not, InsertIntoShiftedVector (dotnet#103725)
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‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2082,6 +2082,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
20822082
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
20832083
break;
20842084
}
2085+
20852086
case NI_Sve_Compute8BitAddresses:
20862087
case NI_Sve_Compute16BitAddresses:
20872088
case NI_Sve_Compute32BitAddresses:
@@ -2095,6 +2096,22 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
20952096
INS_SCALABLE_OPTS_LSL_N);
20962097
break;
20972098
}
2099+
2100+
case NI_Sve_InsertIntoShiftedVector:
2101+
{
2102+
assert(isRMW);
2103+
assert(emitter::isFloatReg(op2Reg) == varTypeIsFloating(intrin.baseType));
2104+
if (targetReg != op1Reg)
2105+
{
2106+
assert(targetReg != op2Reg);
2107+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
2108+
/* canSkip */ true);
2109+
}
2110+
2111+
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
2112+
break;
2113+
}
2114+
20982115
default:
20992116
unreached();
21002117
}

‎src/coreclr/jit/hwintrinsiclistarm64sve.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ HARDWARE_INTRINSIC(Sve, GatherVectorUInt32WithByteOffsetsZeroExtend,
8888
HARDWARE_INTRINSIC(Sve, GatherVectorUInt32ZeroExtend, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1w, INS_invalid, INS_invalid}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
8989
HARDWARE_INTRINSIC(Sve, GatherVectorWithByteOffsets, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1d, INS_sve_ld1d, INS_sve_ld1w, INS_sve_ld1d}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
9090
HARDWARE_INTRINSIC(Sve, GetActiveElementCount, -1, 2, true, {INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_ExplicitMaskedOperation)
91+
HARDWARE_INTRINSIC(Sve, InsertIntoShiftedVector, -1, 2, true, {INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr, INS_sve_insr}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
9192
HARDWARE_INTRINSIC(Sve, LeadingSignCount, -1, -1, false, {INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
9293
HARDWARE_INTRINSIC(Sve, LeadingZeroCount, -1, -1, false, {INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
9394
HARDWARE_INTRINSIC(Sve, LoadVector, -1, 2, true, {INS_sve_ld1b, INS_sve_ld1b, INS_sve_ld1h, INS_sve_ld1h, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1d, INS_sve_ld1d, INS_sve_ld1w, INS_sve_ld1d}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
@@ -159,6 +160,7 @@ HARDWARE_INTRINSIC(Sve, MultiplyBySelectedScalar,
159160
HARDWARE_INTRINSIC(Sve, MultiplyExtended, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmulx, INS_sve_fmulx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
160161
HARDWARE_INTRINSIC(Sve, MultiplySubtract, -1, -1, false, {INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_sve_mls, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)
161162
HARDWARE_INTRINSIC(Sve, Negate, -1, -1, false, {INS_sve_neg, INS_invalid, INS_sve_neg, INS_invalid, INS_sve_neg, INS_invalid, INS_sve_neg, INS_invalid, INS_sve_fneg, INS_sve_fneg}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
163+
HARDWARE_INTRINSIC(Sve, Not, -1, -1, false, {INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation)
162164
HARDWARE_INTRINSIC(Sve, Or, -1, -1, false, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
163165
HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, false, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
164166
HARDWARE_INTRINSIC(Sve, PopCount, -1, -1, false, {INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)

‎src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs‎

Lines changed: 163 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2365,6 +2365,79 @@ internal Arm64() { }
23652365
public static unsafe ulong GetActiveElementCount(Vector<ulong> mask, Vector<ulong> from) { throw new PlatformNotSupportedException(); }
23662366

23672367

2368+
/// Insert scalar into shifted vector
2369+
2370+
/// <summary>
2371+
/// svuint8_t svinsr[_n_u8](svuint8_t op1, uint8_t op2)
2372+
/// INSR Ztied1.B, Wop2
2373+
/// INSR Ztied1.B, Bop2
2374+
/// </summary>
2375+
public static unsafe Vector<byte> InsertIntoShiftedVector(Vector<byte> left, byte right) { throw new PlatformNotSupportedException(); }
2376+
2377+
/// <summary>
2378+
/// svfloat64_t svinsr[_n_f64](svfloat64_t op1, float64_t op2)
2379+
/// INSR Ztied1.D, Xop2
2380+
/// INSR Ztied1.D, Dop2
2381+
/// </summary>
2382+
public static unsafe Vector<double> InsertIntoShiftedVector(Vector<double> left, double right) { throw new PlatformNotSupportedException(); }
2383+
2384+
/// <summary>
2385+
/// svint16_t svinsr[_n_s16](svint16_t op1, int16_t op2)
2386+
/// INSR Ztied1.H, Wop2
2387+
/// INSR Ztied1.H, Hop2
2388+
/// </summary>
2389+
public static unsafe Vector<short> InsertIntoShiftedVector(Vector<short> left, short right) { throw new PlatformNotSupportedException(); }
2390+
2391+
/// <summary>
2392+
/// svint32_t svinsr[_n_s32](svint32_t op1, int32_t op2)
2393+
/// INSR Ztied1.S, Wop2
2394+
/// INSR Ztied1.S, Sop2
2395+
/// </summary>
2396+
public static unsafe Vector<int> InsertIntoShiftedVector(Vector<int> left, int right) { throw new PlatformNotSupportedException(); }
2397+
2398+
/// <summary>
2399+
/// svint64_t svinsr[_n_s64](svint64_t op1, int64_t op2)
2400+
/// INSR Ztied1.D, Xop2
2401+
/// INSR Ztied1.D, Dop2
2402+
/// </summary>
2403+
public static unsafe Vector<long> InsertIntoShiftedVector(Vector<long> left, long right) { throw new PlatformNotSupportedException(); }
2404+
2405+
/// <summary>
2406+
/// svint8_t svinsr[_n_s8](svint8_t op1, int8_t op2)
2407+
/// INSR Ztied1.B, Wop2
2408+
/// INSR Ztied1.B, Bop2
2409+
/// </summary>
2410+
public static unsafe Vector<sbyte> InsertIntoShiftedVector(Vector<sbyte> left, sbyte right) { throw new PlatformNotSupportedException(); }
2411+
2412+
/// <summary>
2413+
/// svfloat32_t svinsr[_n_f32](svfloat32_t op1, float32_t op2)
2414+
/// INSR Ztied1.S, Wop2
2415+
/// INSR Ztied1.S, Sop2
2416+
/// </summary>
2417+
public static unsafe Vector<float> InsertIntoShiftedVector(Vector<float> left, float right) { throw new PlatformNotSupportedException(); }
2418+
2419+
/// <summary>
2420+
/// svuint16_t svinsr[_n_u16](svuint16_t op1, uint16_t op2)
2421+
/// INSR Ztied1.H, Wop2
2422+
/// INSR Ztied1.H, Hop2
2423+
/// </summary>
2424+
public static unsafe Vector<ushort> InsertIntoShiftedVector(Vector<ushort> left, ushort right) { throw new PlatformNotSupportedException(); }
2425+
2426+
/// <summary>
2427+
/// svuint32_t svinsr[_n_u32](svuint32_t op1, uint32_t op2)
2428+
/// INSR Ztied1.S, Wop2
2429+
/// INSR Ztied1.S, Sop2
2430+
/// </summary>
2431+
public static unsafe Vector<uint> InsertIntoShiftedVector(Vector<uint> left, uint right) { throw new PlatformNotSupportedException(); }
2432+
2433+
/// <summary>
2434+
/// svuint64_t svinsr[_n_u64](svuint64_t op1, uint64_t op2)
2435+
/// INSR Ztied1.D, Xop2
2436+
/// INSR Ztied1.D, Dop2
2437+
/// </summary>
2438+
public static unsafe Vector<ulong> InsertIntoShiftedVector(Vector<ulong> left, ulong right) { throw new PlatformNotSupportedException(); }
2439+
2440+
23682441
/// Count leading sign bits
23692442

23702443
/// <summary>
@@ -4034,6 +4107,96 @@ internal Arm64() { }
40344107
/// </summary>
40354108
public static unsafe Vector<float> Negate(Vector<float> value) { throw new PlatformNotSupportedException(); }
40364109

4110+
/// Bitwise invert
4111+
4112+
/// <summary>
4113+
/// svuint8_t svnot[_u8]_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
4114+
/// NOT Ztied.B, Pg/M, Zop.B
4115+
/// svuint8_t svnot[_u8]_x(svbool_t pg, svuint8_t op)
4116+
/// NOT Ztied.B, Pg/M, Ztied.B
4117+
/// svuint8_t svnot[_u8]_z(svbool_t pg, svuint8_t op)
4118+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4119+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4120+
/// </summary>
4121+
public static unsafe Vector<byte> Not(Vector<byte> value) { throw new PlatformNotSupportedException(); }
4122+
4123+
/// <summary>
4124+
/// svint16_t svnot[_s16]_m(svint16_t inactive, svbool_t pg, svint16_t op)
4125+
/// NOT Ztied.H, Pg/M, Zop.H
4126+
/// svint16_t svnot[_s16]_x(svbool_t pg, svint16_t op)
4127+
/// NOT Ztied.H, Pg/M, Ztied.H
4128+
/// svint16_t svnot[_s16]_z(svbool_t pg, svint16_t op)
4129+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4130+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4131+
/// </summary>
4132+
public static unsafe Vector<short> Not(Vector<short> value) { throw new PlatformNotSupportedException(); }
4133+
4134+
/// <summary>
4135+
/// svint32_t svnot[_s32]_m(svint32_t inactive, svbool_t pg, svint32_t op)
4136+
/// NOT Ztied.S, Pg/M, Zop.S
4137+
/// svint32_t svnot[_s32]_x(svbool_t pg, svint32_t op)
4138+
/// NOT Ztied.S, Pg/M, Ztied.S
4139+
/// svint32_t svnot[_s32]_z(svbool_t pg, svint32_t op)
4140+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4141+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4142+
/// </summary>
4143+
public static unsafe Vector<int> Not(Vector<int> value) { throw new PlatformNotSupportedException(); }
4144+
4145+
/// <summary>
4146+
/// svint64_t svnot[_s64]_m(svint64_t inactive, svbool_t pg, svint64_t op)
4147+
/// NOT Ztied.D, Pg/M, Zop.D
4148+
/// svint64_t svnot[_s64]_x(svbool_t pg, svint64_t op)
4149+
/// NOT Ztied.D, Pg/M, Ztied.D
4150+
/// svint64_t svnot[_s64]_z(svbool_t pg, svint64_t op)
4151+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4152+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4153+
/// </summary>
4154+
public static unsafe Vector<long> Not(Vector<long> value) { throw new PlatformNotSupportedException(); }
4155+
4156+
/// <summary>
4157+
/// svint8_t svnot[_s8]_m(svint8_t inactive, svbool_t pg, svint8_t op)
4158+
/// NOT Ztied.B, Pg/M, Zop.B
4159+
/// svint8_t svnot[_s8]_x(svbool_t pg, svint8_t op)
4160+
/// NOT Ztied.B, Pg/M, Ztied.B
4161+
/// svint8_t svnot[_s8]_z(svbool_t pg, svint8_t op)
4162+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4163+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4164+
/// </summary>
4165+
public static unsafe Vector<sbyte> Not(Vector<sbyte> value) { throw new PlatformNotSupportedException(); }
4166+
4167+
/// <summary>
4168+
/// svuint16_t svnot[_u16]_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
4169+
/// NOT Ztied.H, Pg/M, Zop.H
4170+
/// svuint16_t svnot[_u16]_x(svbool_t pg, svuint16_t op)
4171+
/// NOT Ztied.H, Pg/M, Ztied.H
4172+
/// svuint16_t svnot[_u16]_z(svbool_t pg, svuint16_t op)
4173+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4174+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4175+
/// </summary>
4176+
public static unsafe Vector<ushort> Not(Vector<ushort> value) { throw new PlatformNotSupportedException(); }
4177+
4178+
/// <summary>
4179+
/// svuint32_t svnot[_u32]_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
4180+
/// NOT Ztied.S, Pg/M, Zop.S
4181+
/// svuint32_t svnot[_u32]_x(svbool_t pg, svuint32_t op)
4182+
/// NOT Ztied.S, Pg/M, Ztied.S
4183+
/// svuint32_t svnot[_u32]_z(svbool_t pg, svuint32_t op)
4184+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4185+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4186+
/// </summary>
4187+
public static unsafe Vector<uint> Not(Vector<uint> value) { throw new PlatformNotSupportedException(); }
4188+
4189+
/// <summary>
4190+
/// svuint64_t svnot[_u64]_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
4191+
/// NOT Ztied.D, Pg/M, Zop.D
4192+
/// svuint64_t svnot[_u64]_x(svbool_t pg, svuint64_t op)
4193+
/// NOT Ztied.D, Pg/M, Ztied.D
4194+
/// svuint64_t svnot[_u64]_z(svbool_t pg, svuint64_t op)
4195+
/// svbool_t svnot[_b]_z(svbool_t pg, svbool_t op)
4196+
/// EOR Presult.B, Pg/Z, Pop.B, Pg.B
4197+
/// </summary>
4198+
public static unsafe Vector<ulong> Not(Vector<ulong> value) { throw new PlatformNotSupportedException(); }
4199+
40374200
/// Or : Bitwise inclusive OR
40384201

40394202
/// <summary>

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