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alexcrichtonalexcrichton
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Rename bmi to bmi1
In accordance with rust-lang/rust#48565
1 parent 78dd56a commit 678cbd3

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6 files changed

+33
-41
lines changed

6 files changed

+33
-41
lines changed

‎coresimd/x86/bmi.rs‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ use stdsimd_test::assert_instr;
1515
/// Extracts bits in range [`start`, `start` + `length`) from `a` into
1616
/// the least significant bits of the result.
1717
#[inline]
18-
#[target_feature(enable = "bmi")]
18+
#[target_feature(enable = "bmi1")]
1919
#[cfg_attr(test, assert_instr(bextr))]
2020
pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
2121
_bextr2_u32(a, (start & 0xff_u32) | ((len & 0xff_u32) << 8_u32))
@@ -27,31 +27,31 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
2727
/// Bits [7,0] of `control` specify the index to the first bit in the range to
2828
/// be extracted, and bits [15,8] specify the length of the range.
2929
#[inline]
30-
#[target_feature(enable = "bmi")]
30+
#[target_feature(enable = "bmi1")]
3131
#[cfg_attr(test, assert_instr(bextr))]
3232
pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 {
3333
x86_bmi_bextr_32(a, control)
3434
}
3535

3636
/// Bitwise logical `AND` of inverted `a` with `b`.
3737
#[inline]
38-
#[target_feature(enable = "bmi")]
38+
#[target_feature(enable = "bmi1")]
3939
#[cfg_attr(test, assert_instr(andn))]
4040
pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 {
4141
!a & b
4242
}
4343

4444
/// Extract lowest set isolated bit.
4545
#[inline]
46-
#[target_feature(enable = "bmi")]
46+
#[target_feature(enable = "bmi1")]
4747
#[cfg_attr(test, assert_instr(blsi))]
4848
pub unsafe fn _blsi_u32(x: u32) -> u32 {
4949
x & x.wrapping_neg()
5050
}
5151

5252
/// Get mask up to lowest set bit.
5353
#[inline]
54-
#[target_feature(enable = "bmi")]
54+
#[target_feature(enable = "bmi1")]
5555
#[cfg_attr(test, assert_instr(blsmsk))]
5656
pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
5757
x ^ (x.wrapping_sub(1_u32))
@@ -61,7 +61,7 @@ pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
6161
///
6262
/// If `x` is sets CF.
6363
#[inline]
64-
#[target_feature(enable = "bmi")]
64+
#[target_feature(enable = "bmi1")]
6565
#[cfg_attr(test, assert_instr(blsr))]
6666
pub unsafe fn _blsr_u32(x: u32) -> u32 {
6767
x & (x.wrapping_sub(1))
@@ -71,7 +71,7 @@ pub unsafe fn _blsr_u32(x: u32) -> u32 {
7171
///
7272
/// When the source operand is 0, it returns its size in bits.
7373
#[inline]
74-
#[target_feature(enable = "bmi")]
74+
#[target_feature(enable = "bmi1")]
7575
#[cfg_attr(test, assert_instr(tzcnt))]
7676
pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
7777
x.trailing_zeros()
@@ -81,7 +81,7 @@ pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
8181
///
8282
/// When the source operand is 0, it returns its size in bits.
8383
#[inline]
84-
#[target_feature(enable = "bmi")]
84+
#[target_feature(enable = "bmi1")]
8585
#[cfg_attr(test, assert_instr(tzcnt))]
8686
pub unsafe fn _mm_tzcnt_32(x: u32) -> i32 {
8787
x.trailing_zeros() as i32
@@ -98,13 +98,13 @@ mod tests {
9898

9999
use coresimd::x86::*;
100100

101-
#[simd_test = "bmi"]
101+
#[simd_test = "bmi1"]
102102
unsafe fn test_bextr_u32() {
103103
let r = _bextr_u32(0b0101_0000u32, 4, 4);
104104
assert_eq!(r, 0b0000_0101u32);
105105
}
106106

107-
#[simd_test = "bmi"]
107+
#[simd_test = "bmi1"]
108108
unsafe fn test_andn_u32() {
109109
assert_eq!(_andn_u32(0, 0), 0);
110110
assert_eq!(_andn_u32(0, 1), 1);
@@ -127,25 +127,25 @@ mod tests {
127127
assert_eq!(r, 0b0001_1101u32);
128128
}
129129

130-
#[simd_test = "bmi"]
130+
#[simd_test = "bmi1"]
131131
unsafe fn test_blsi_u32() {
132132
assert_eq!(_blsi_u32(0b1101_0000u32), 0b0001_0000u32);
133133
}
134134

135-
#[simd_test = "bmi"]
135+
#[simd_test = "bmi1"]
136136
unsafe fn test_blsmsk_u32() {
137137
let r = _blsmsk_u32(0b0011_0000u32);
138138
assert_eq!(r, 0b0001_1111u32);
139139
}
140140

141-
#[simd_test = "bmi"]
141+
#[simd_test = "bmi1"]
142142
unsafe fn test_blsr_u32() {
143143
// TODO: test the behavior when the input is 0
144144
let r = _blsr_u32(0b0011_0000u32);
145145
assert_eq!(r, 0b0010_0000u32);
146146
}
147147

148-
#[simd_test = "bmi"]
148+
#[simd_test = "bmi1"]
149149
unsafe fn test_tzcnt_u32() {
150150
assert_eq!(_tzcnt_u32(0b0000_0001u32), 0u32);
151151
assert_eq!(_tzcnt_u32(0b0000_0000u32), 32u32);

‎coresimd/x86_64/bmi.rs‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ use stdsimd_test::assert_instr;
1515
/// Extracts bits in range [`start`, `start` + `length`) from `a` into
1616
/// the least significant bits of the result.
1717
#[inline]
18-
#[target_feature(enable = "bmi")]
18+
#[target_feature(enable = "bmi1")]
1919
#[cfg_attr(test, assert_instr(bextr))]
2020
#[cfg(not(target_arch = "x86"))]
2121
pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
@@ -28,7 +28,7 @@ pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
2828
/// Bits [7,0] of `control` specify the index to the first bit in the range to
2929
/// be extracted, and bits [15,8] specify the length of the range.
3030
#[inline]
31-
#[target_feature(enable = "bmi")]
31+
#[target_feature(enable = "bmi1")]
3232
#[cfg_attr(test, assert_instr(bextr))]
3333
#[cfg(not(target_arch = "x86"))]
3434
pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
@@ -37,15 +37,15 @@ pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
3737

3838
/// Bitwise logical `AND` of inverted `a` with `b`.
3939
#[inline]
40-
#[target_feature(enable = "bmi")]
40+
#[target_feature(enable = "bmi1")]
4141
#[cfg_attr(test, assert_instr(andn))]
4242
pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 {
4343
!a & b
4444
}
4545

4646
/// Extract lowest set isolated bit.
4747
#[inline]
48-
#[target_feature(enable = "bmi")]
48+
#[target_feature(enable = "bmi1")]
4949
#[cfg_attr(test, assert_instr(blsi))]
5050
#[cfg(not(target_arch = "x86"))] // generates lots of instructions
5151
pub unsafe fn _blsi_u64(x: u64) -> u64 {
@@ -54,7 +54,7 @@ pub unsafe fn _blsi_u64(x: u64) -> u64 {
5454

5555
/// Get mask up to lowest set bit.
5656
#[inline]
57-
#[target_feature(enable = "bmi")]
57+
#[target_feature(enable = "bmi1")]
5858
#[cfg_attr(test, assert_instr(blsmsk))]
5959
#[cfg(not(target_arch = "x86"))] // generates lots of instructions
6060
pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
@@ -65,7 +65,7 @@ pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
6565
///
6666
/// If `x` is sets CF.
6767
#[inline]
68-
#[target_feature(enable = "bmi")]
68+
#[target_feature(enable = "bmi1")]
6969
#[cfg_attr(test, assert_instr(blsr))]
7070
#[cfg(not(target_arch = "x86"))] // generates lots of instructions
7171
pub unsafe fn _blsr_u64(x: u64) -> u64 {
@@ -76,7 +76,7 @@ pub unsafe fn _blsr_u64(x: u64) -> u64 {
7676
///
7777
/// When the source operand is 0, it returns its size in bits.
7878
#[inline]
79-
#[target_feature(enable = "bmi")]
79+
#[target_feature(enable = "bmi1")]
8080
#[cfg_attr(test, assert_instr(tzcnt))]
8181
pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
8282
x.trailing_zeros() as u64
@@ -86,7 +86,7 @@ pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
8686
///
8787
/// When the source operand is 0, it returns its size in bits.
8888
#[inline]
89-
#[target_feature(enable = "bmi")]
89+
#[target_feature(enable = "bmi1")]
9090
#[cfg_attr(test, assert_instr(tzcnt))]
9191
pub unsafe fn _mm_tzcnt_64(x: u64) -> i64 {
9292
x.trailing_zeros() as i64
@@ -104,13 +104,13 @@ mod tests {
104104
use coresimd::x86::*;
105105
use coresimd::x86_64::*;
106106

107-
#[simd_test = "bmi"]
107+
#[simd_test = "bmi1"]
108108
unsafe fn test_bextr_u64() {
109109
let r = _bextr_u64(0b0101_0000u64, 4, 4);
110110
assert_eq!(r, 0b0000_0101u64);
111111
}
112112

113-
#[simd_test = "bmi"]
113+
#[simd_test = "bmi1"]
114114
unsafe fn test_andn_u64() {
115115
assert_eq!(_andn_u64(0, 0), 0);
116116
assert_eq!(_andn_u64(0, 1), 1);
@@ -133,25 +133,25 @@ mod tests {
133133
assert_eq!(r, 0b0001_1101u64);
134134
}
135135

136-
#[simd_test = "bmi"]
136+
#[simd_test = "bmi1"]
137137
unsafe fn test_blsi_u64() {
138138
assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
139139
}
140140

141-
#[simd_test = "bmi"]
141+
#[simd_test = "bmi1"]
142142
unsafe fn test_blsmsk_u64() {
143143
let r = _blsmsk_u64(0b0011_0000u64);
144144
assert_eq!(r, 0b0001_1111u64);
145145
}
146146

147-
#[simd_test = "bmi"]
147+
#[simd_test = "bmi1"]
148148
unsafe fn test_blsr_u64() {
149149
// TODO: test the behavior when the input is 0
150150
let r = _blsr_u64(0b0011_0000u64);
151151
assert_eq!(r, 0b0010_0000u64);
152152
}
153153

154-
#[simd_test = "bmi"]
154+
#[simd_test = "bmi1"]
155155
unsafe fn test_tzcnt_u64() {
156156
assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64);
157157
assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64);

‎crates/coresimd/tests/cpu-detection.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ fn x86_all() {
3434
);
3535
println!("fma: {:?}", is_target_feature_detected!("fma"));
3636
println!("abm: {:?}", is_target_feature_detected!("abm"));
37-
println!("bmi: {:?}", is_target_feature_detected!("bmi"));
37+
println!("bmi: {:?}", is_target_feature_detected!("bmi1"));
3838
println!("bmi2: {:?}", is_target_feature_detected!("bmi2"));
3939
println!("tbm: {:?}", is_target_feature_detected!("tbm"));
4040
println!("popcnt: {:?}", is_target_feature_detected!("popcnt"));

‎crates/stdsimd-verify/tests/x86-intel.rs‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -249,14 +249,6 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
249249
.flat_map(|c| c.to_lowercase())
250250
.collect::<String>();
251251

252-
// Normalize `bmi1` to `bmi` as apparently that's what we're
253-
// calling it.
254-
let cpuid = if cpuid == "bmi1" {
255-
String::from("bmi")
256-
} else {
257-
cpuid
258-
};
259-
260252
let rust_feature = rust.target_feature
261253
.expect(&format!("no target feature listed for {}", rust.name));
262254
if rust_feature.contains(&cpuid) {

‎crates/stdsimd/tests/cpu-detection.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ fn x86_all() {
5959
);
6060
println!("fma: {:?}", is_target_feature_detected!("fma"));
6161
println!("abm: {:?}", is_target_feature_detected!("abm"));
62-
println!("bmi: {:?}", is_target_feature_detected!("bmi"));
62+
println!("bmi: {:?}", is_target_feature_detected!("bmi1"));
6363
println!("bmi2: {:?}", is_target_feature_detected!("bmi2"));
6464
println!("tbm: {:?}", is_target_feature_detected!("tbm"));
6565
println!("popcnt: {:?}", is_target_feature_detected!("popcnt"));

‎stdsimd/arch/detect/x86.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ macro_rules! is_target_feature_detected {
125125
$crate::arch::detect::check_for(
126126
$crate::arch::detect::Feature::fma)
127127
};
128-
("bmi") => {
128+
("bmi1") => {
129129
$crate::arch::detect::check_for(
130130
$crate::arch::detect::Feature::bmi)
131131
};
@@ -504,7 +504,7 @@ mod tests {
504504
);
505505
println!("fma: {:?}", is_target_feature_detected!("fma"));
506506
println!("abm: {:?}", is_target_feature_detected!("abm"));
507-
println!("bmi: {:?}", is_target_feature_detected!("bmi"));
507+
println!("bmi: {:?}", is_target_feature_detected!("bmi1"));
508508
println!("bmi2: {:?}", is_target_feature_detected!("bmi2"));
509509
println!("tbm: {:?}", is_target_feature_detected!("tbm"));
510510
println!("popcnt: {:?}", is_target_feature_detected!("popcnt"));
@@ -553,7 +553,7 @@ mod tests {
553553
information.avx512_vpopcntdq()
554554
);
555555
assert_eq!(is_target_feature_detected!("fma"), information.fma());
556-
assert_eq!(is_target_feature_detected!("bmi"), information.bmi1());
556+
assert_eq!(is_target_feature_detected!("bmi1"), information.bmi1());
557557
assert_eq!(is_target_feature_detected!("bmi2"), information.bmi2());
558558
assert_eq!(is_target_feature_detected!("popcnt"), information.popcnt());
559559
assert_eq!(is_target_feature_detected!("abm"), information.lzcnt());

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