remove rustdoc warnings

Author: GuillaumeGomez

coresimd/x86/avx.rs

@@ -1950,7 +1950,7 @@ pub unsafe fn _mm256_stream_si256(mem_addr: *const __m256i, a: __m256i) {
     intrinsics::nontemporal_store(mem::transmute(mem_addr), a);
 }
 
-/// Moves double-precision values from a 256-bit vector of [4 x double]
+/// Moves double-precision values from a 256-bit vector of `[4 x double]`
 /// to a 32-byte aligned memory location. To minimize caching, the data is
 /// flagged as non-temporal (unlikely to be used again soon).
 ///
@@ -1964,7 +1964,7 @@ pub unsafe fn _mm256_stream_pd(mem_addr: *const f64, a: __m256d) {
 }
 
 /// Moves single-precision floating point values from a 256-bit vector
-/// of [8 x float] to a 32-byte aligned memory location. To minimize
+/// of `[8 x float]` to a 32-byte aligned memory location. To minimize
 /// caching, the data is flagged as non-temporal (unlikely to be used again
 /// soon).
 ///
@@ -2791,8 +2791,8 @@ pub unsafe fn _mm256_castsi128_si256(a: __m128i) -> __m256i {
     mem::transmute(dst)
 }
 
-/// Constructs a 256-bit floating-point vector of [8 x float] from a
-/// 128-bit floating-point vector of [4 x float]. The lower 128 bits contain
+/// Constructs a 256-bit floating-point vector of `[8 x float]` from a
+/// 128-bit floating-point vector of `[4 x float]`. The lower 128 bits contain
 /// the value of the source vector. The upper 128 bits are set to zero.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextps128_ps256)
@@ -2821,8 +2821,8 @@ pub unsafe fn _mm256_zextsi128_si256(a: __m128i) -> __m256i {
     mem::transmute(dst)
 }
 
-/// Constructs a 256-bit floating-point vector of [4 x double] from a
-/// 128-bit floating-point vector of [2 x double]. The lower 128 bits
+/// Constructs a 256-bit floating-point vector of `[4 x double]` from a
+/// 128-bit floating-point vector of `[2 x double]`. The lower 128 bits
 /// contain the value of the source vector. The upper 128 bits are set
 /// to zero.
 ///
@@ -3045,7 +3045,7 @@ pub unsafe fn _mm256_storeu2_m128i(
     _mm_storeu_si128(hiaddr, hi);
 }
 
-/// Returns the first element of the input vector of [8 x float].
+/// Returns the first element of the input vector of `[8 x float]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtss_f32)
 #[inline]

coresimd/x86/avx2.rs

@@ -2506,7 +2506,7 @@ pub unsafe fn _mm256_mullo_epi32(a: __m256i, b: __m256i) -> __m256i {
 /// Multiply packed 16-bit integers in `a` and `b`, producing
 /// intermediate signed 32-bit integers. Truncate each intermediate
 /// integer to the 18 most significant bits, round by adding 1, and
-/// return bits [16:1]
+/// return bits `[16:1]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mulhrs_epi16)
 #[inline]
@@ -4001,7 +4001,7 @@ pub unsafe fn _mm256_extract_epi32(a: __m256i, imm8: i32) -> i32 {
     simd_extract(a.as_i32x8(), imm8)
 }
 
-/// Returns the first element of the input vector of [4 x double].
+/// Returns the first element of the input vector of `[4 x double]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsd_f64)
 #[inline]
@@ -4012,7 +4012,7 @@ pub unsafe fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
     simd_extract(a, 0)
 }
 
-/// Returns the first element of the input vector of [8 x i32].
+/// Returns the first element of the input vector of `[8 x i32]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsi256_si32)
 #[inline]

coresimd/x86/bmi1.rs

@@ -30,8 +30,8 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
 /// Extracts bits of `a` specified by `control` into
 /// the least significant bits of the result.
 ///
-/// Bits [7,0] of `control` specify the index to the first bit in the range to
-/// be extracted, and bits [15,8] specify the length of the range.
+/// Bits `[7,0]` of `control` specify the index to the first bit in the range to
+/// be extracted, and bits `[15,8]` specify the length of the range.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr2_u32)
 #[inline]

coresimd/x86/sse.rs

@@ -2212,7 +2212,7 @@ pub unsafe fn _m_pavgw(a: __m64, b: __m64) -> __m64 {
 /// Subtracts the corresponding 8-bit unsigned integer values of the two
 /// 64-bit vector operands and computes the absolute value for each of the
 /// difference. Then sum of the 8 absolute differences is written to the
-/// bits [15:0] of the destination; the remaining bits [63:16] are cleared.
+/// bits `[15:0]` of the destination; the remaining bits `[63:16]` are cleared.
 #[inline]
 #[target_feature(enable = "sse,mmx")]
 #[cfg_attr(test, assert_instr(psadbw))]
@@ -2223,15 +2223,15 @@ pub unsafe fn _mm_sad_pu8(a: __m64, b: __m64) -> __m64 {
 /// Subtracts the corresponding 8-bit unsigned integer values of the two
 /// 64-bit vector operands and computes the absolute value for each of the
 /// difference. Then sum of the 8 absolute differences is written to the
-/// bits [15:0] of the destination; the remaining bits [63:16] are cleared.
+/// bits `[15:0]` of the destination; the remaining bits `[63:16]` are cleared.
 #[inline]
 #[target_feature(enable = "sse,mmx")]
 #[cfg_attr(test, assert_instr(psadbw))]
 pub unsafe fn _m_psadbw(a: __m64, b: __m64) -> __m64 {
     _mm_sad_pu8(a, b)
 }
 
-/// Converts two elements of a 64-bit vector of [2 x i32] into two
+/// Converts two elements of a 64-bit vector of `[2 x i32]` into two
 /// floating point values and writes them to the lower 64-bits of the
 /// destination. The remaining higher order elements of the destination are
 /// copied from the corresponding elements in the first operand.
@@ -2242,7 +2242,7 @@ pub unsafe fn _mm_cvtpi32_ps(a: __m128, b: __m64) -> __m128 {
     cvtpi2ps(a, b)
 }
 
-/// Converts two elements of a 64-bit vector of [2 x i32] into two
+/// Converts two elements of a 64-bit vector of `[2 x i32]` into two
 /// floating point values and writes them to the lower 64-bits of the
 /// destination. The remaining higher order elements of the destination are
 /// copied from the corresponding elements in the first operand.
@@ -2304,7 +2304,7 @@ pub unsafe fn _mm_cvtpu16_ps(a: __m64) -> __m128 {
 }
 
 /// Converts the two 32-bit signed integer values from each 64-bit vector
-/// operand of [2 x i32] into a 128-bit vector of [4 x float].
+/// operand of `[2 x i32]` into a 128-bit vector of `[4 x float]`.
 #[inline]
 #[target_feature(enable = "sse,mmx")]
 #[cfg_attr(test, assert_instr(cvtpi2ps))]
@@ -2343,7 +2343,7 @@ pub unsafe fn _m_maskmovq(a: __m64, mask: __m64, mem_addr: *mut i8) {
     _mm_maskmove_si64(a, mask, mem_addr)
 }
 
-/// Extracts 16-bit element from a 64-bit vector of [4 x i16] and
+/// Extracts 16-bit element from a 64-bit vector of `[4 x i16]` and
 /// returns it, as specified by the immediate integer operand.
 #[inline]
 #[target_feature(enable = "sse,mmx")]
@@ -2358,7 +2358,7 @@ pub unsafe fn _mm_extract_pi16(a: __m64, imm2: i32) -> i32 {
     constify_imm2!(imm2, call)
 }
 
-/// Extracts 16-bit element from a 64-bit vector of [4 x i16] and
+/// Extracts 16-bit element from a 64-bit vector of `[4 x i16]` and
 /// returns it, as specified by the immediate integer operand.
 #[inline]
 #[target_feature(enable = "sse,mmx")]
@@ -2373,7 +2373,7 @@ pub unsafe fn _m_pextrw(a: __m64, imm2: i32) -> i32 {
     constify_imm2!(imm2, call)
 }
 
-/// Copies data from the 64-bit vector of [4 x i16] to the destination,
+/// Copies data from the 64-bit vector of `[4 x i16]` to the destination,
 /// and inserts the lower 16-bits of an integer operand at the 16-bit offset
 /// specified by the immediate operand `n`.
 #[inline]
@@ -2389,7 +2389,7 @@ pub unsafe fn _mm_insert_pi16(a: __m64, d: i32, imm2: i32) -> __m64 {
     constify_imm2!(imm2, call)
 }
 
-/// Copies data from the 64-bit vector of [4 x i16] to the destination,
+/// Copies data from the 64-bit vector of `[4 x i16]` to the destination,
 /// and inserts the lower 16-bits of an integer operand at the 16-bit offset
 /// specified by the immediate operand `n`.
 #[inline]

coresimd/x86/sse2.rs

@@ -2561,7 +2561,7 @@ pub unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d {
 }
 
 /// Loads a double-precision value into the high-order bits of a 128-bit
-/// vector of [2 x double]. The low-order bits are copied from the low-order
+/// vector of `[2 x double]`. The low-order bits are copied from the low-order
 /// bits of the first operand.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadh_pd)
@@ -2574,7 +2574,7 @@ pub unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
 }
 
 /// Loads a double-precision value into the low-order bits of a 128-bit
-/// vector of [2 x double]. The high-order bits are copied from the
+/// vector of `[2 x double]`. The high-order bits are copied from the
 /// high-order bits of the first operand.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadl_pd)
@@ -2586,7 +2586,7 @@ pub unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
     _mm_setr_pd(*mem_addr, simd_extract(a, 1))
 }
 
-/// Stores a 128-bit floating point vector of [2 x double] to a 128-bit
+/// Stores a 128-bit floating point vector of `[2 x double]` to a 128-bit
 /// aligned memory location.
 /// To minimize caching, the data is flagged as non-temporal (unlikely to be
 /// used again soon).
@@ -2600,7 +2600,7 @@ pub unsafe fn _mm_stream_pd(mem_addr: *mut f64, a: __m128d) {
     intrinsics::nontemporal_store(mem::transmute(mem_addr), a);
 }
 
-/// Stores the lower 64 bits of a 128-bit vector of [2 x double] to a
+/// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a
 /// memory location.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_sd)
@@ -2678,7 +2678,7 @@ pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
     *(mem_addr as *mut __m128d) = b;
 }
 
-/// Stores the upper 64 bits of a 128-bit vector of [2 x double] to a
+/// Stores the upper 64 bits of a 128-bit vector of `[2 x double]` to a
 /// memory location.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeh_pd)
@@ -2690,7 +2690,7 @@ pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
     *mem_addr = simd_extract(a, 1);
 }
 
-/// Stores the lower 64 bits of a 128-bit vector of [2 x double] to a
+/// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a
 /// memory location.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storel_pd)
@@ -2760,8 +2760,8 @@ pub unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d {
     dst
 }
 
-/// Constructs a 128-bit floating-point vector of [2 x double] from two
-/// 128-bit vector parameters of [2 x double], using the immediate-value
+/// Constructs a 128-bit floating-point vector of `[2 x double]` from two
+/// 128-bit vector parameters of `[2 x double]`, using the immediate-value
 /// parameter as a specifier.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_pd)
@@ -2779,7 +2779,7 @@ pub unsafe fn _mm_shuffle_pd(a: __m128d, b: __m128d, imm8: i32) -> __m128d {
     }
 }
 
-/// Constructs a 128-bit floating-point vector of [2 x double]. The lower
+/// Constructs a 128-bit floating-point vector of `[2 x double]`. The lower
 /// 64 bits are set to the lower 64 bits of the second parameter. The upper
 /// 64 bits are set to the upper 64 bits of the first parameter.
 ///
@@ -2792,8 +2792,8 @@ pub unsafe fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d {
     _mm_setr_pd(simd_extract(b, 0), simd_extract(a, 1))
 }
 
-/// Casts a 128-bit floating-point vector of [2 x double] into a 128-bit
-/// floating-point vector of [4 x float].
+/// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit
+/// floating-point vector of `[4 x float]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ps)
 #[inline]
@@ -2803,7 +2803,7 @@ pub unsafe fn _mm_castpd_ps(a: __m128d) -> __m128 {
     mem::transmute(a)
 }
 
-/// Casts a 128-bit floating-point vector of [2 x double] into a 128-bit
+/// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit
 /// integer vector.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_si128)
@@ -2814,8 +2814,8 @@ pub unsafe fn _mm_castpd_si128(a: __m128d) -> __m128i {
     mem::transmute::<i64x2, _>(simd_cast(a))
 }
 
-/// Casts a 128-bit floating-point vector of [4 x float] into a 128-bit
-/// floating-point vector of [2 x double].
+/// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit
+/// floating-point vector of `[2 x double]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_pd)
 #[inline]
@@ -2825,7 +2825,7 @@ pub unsafe fn _mm_castps_pd(a: __m128) -> __m128d {
     mem::transmute(a)
 }
 
-/// Casts a 128-bit floating-point vector of [4 x float] into a 128-bit
+/// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit
 /// integer vector.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_si128)
@@ -2837,7 +2837,7 @@ pub unsafe fn _mm_castps_si128(a: __m128) -> __m128i {
 }
 
 /// Casts a 128-bit integer vector into a 128-bit floating-point vector
-/// of [2 x double].
+/// of `[2 x double]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_pd)
 #[inline]
@@ -2848,7 +2848,7 @@ pub unsafe fn _mm_castsi128_pd(a: __m128i) -> __m128d {
 }
 
 /// Casts a 128-bit integer vector into a 128-bit floating-point vector
-/// of [4 x float].
+/// of `[4 x float]`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ps)
 #[inline]
@@ -2881,8 +2881,8 @@ pub unsafe fn _mm_undefined_si128() -> __m128i {
 /// The resulting `__m128d` element is composed by the low-order values of
 /// the two `__m128d` interleaved input elements, i.e.:
 ///
-/// * The [127:64] bits are copied from the [127:64] bits of the second input
-/// * The [63:0] bits are copied from the [127:64] bits of the first input
+/// * The `[127:64]` bits are copied from the `[127:64]` bits of the second input
+/// * The `[63:0]` bits are copied from the `[127:64]` bits of the first input
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_pd)
 #[inline]
@@ -2896,8 +2896,8 @@ pub unsafe fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
 /// The resulting `__m128d` element is composed by the high-order values of
 /// the two `__m128d` interleaved input elements, i.e.:
 ///
-/// * The [127:64] bits are copied from the [63:0] bits of the second input
-/// * The [63:0] bits are copied from the [63:0] bits of the first input
+/// * The `[127:64]` bits are copied from the `[63:0]` bits of the second input
+/// * The `[63:0]` bits are copied from the `[63:0]` bits of the first input
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_pd)
 #[inline]
@@ -2937,16 +2937,16 @@ pub unsafe fn _mm_sub_si64(a: __m64, b: __m64) -> __m64 {
 }
 
 /// Converts the two signed 32-bit integer elements of a 64-bit vector of
-/// [2 x i32] into two double-precision floating-point values, returned in a
-/// 128-bit vector of [2 x double].
+/// `[2 x i32]` into two double-precision floating-point values, returned in a
+/// 128-bit vector of `[2 x double]`.
 #[inline]
 #[target_feature(enable = "sse2,mmx")]
 #[cfg_attr(test, assert_instr(cvtpi2pd))]
 pub unsafe fn _mm_cvtpi32_pd(a: __m64) -> __m128d {
     cvtpi2pd(a)
 }
 
-/// Initializes both 64-bit values in a 128-bit vector of [2 x i64] with
+/// Initializes both 64-bit values in a 128-bit vector of `[2 x i64]` with
 /// the specified 64-bit integer values.
 #[inline]
 #[target_feature(enable = "sse2,mmx")]
@@ -2955,7 +2955,7 @@ pub unsafe fn _mm_set_epi64(e1: __m64, e0: __m64) -> __m128i {
     _mm_set_epi64x(mem::transmute(e1), mem::transmute(e0))
 }
 
-/// Initializes both values in a 128-bit vector of [2 x i64] with the
+/// Initializes both values in a 128-bit vector of `[2 x i64]` with the
 /// specified 64-bit value.
 #[inline]
 #[target_feature(enable = "sse2,mmx")]
@@ -2994,8 +2994,8 @@ pub unsafe fn _mm_movpi64_epi64(a: __m64) -> __m128i {
 }
 
 /// Converts the two double-precision floating-point elements of a
-/// 128-bit vector of [2 x double] into two signed 32-bit integer values,
-/// returned in a 64-bit vector of [2 x i32].
+/// 128-bit vector of `[2 x double]` into two signed 32-bit integer values,
+/// returned in a 64-bit vector of `[2 x i32]`.
 #[inline]
 #[target_feature(enable = "sse2,mmx")]
 #[cfg_attr(test, assert_instr(cvtpd2pi))]
@@ -3004,8 +3004,8 @@ pub unsafe fn _mm_cvtpd_pi32(a: __m128d) -> __m64 {
 }
 
 /// Converts the two double-precision floating-point elements of a
-/// 128-bit vector of [2 x double] into two signed 32-bit integer values,
-/// returned in a 64-bit vector of [2 x i32].
+/// 128-bit vector of `[2 x double]` into two signed 32-bit integer values,
+/// returned in a 64-bit vector of `[2 x i32]`.
 /// If the result of either conversion is inexact, the result is truncated
 /// (rounded towards zero) regardless of the current MXCSR setting.
 #[inline]

coresimd/x86/sse4a.rs

@@ -24,8 +24,8 @@ extern "C" {
 
 /// Extracts the bit range specified by `y` from the lower 64 bits of `x`.
 ///
-/// The [13:8] bits of `y` specify the index of the bit-range to extract. The
-/// [5:0] bits of `y` specify the length of the bit-range to extract. All other
+/// The `[13:8]` bits of `y` specify the index of the bit-range to extract. The
+/// `[5:0]` bits of `y` specify the length of the bit-range to extract. All other
 /// bits are ignored.
 ///
 /// If the length is zero, it is interpreted as `64`. If the length and index