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This commit performs various improvements (better register allocation,
less register clobbering on the worst case and better readability) of
RISC-V inline assembly use cases.
Note that it does not change the `p` module (which defines the "P"
extension draft instructions but very likely to change).
1. Use `lateout` as possible.
Unlike `out(reg)` and `in(reg)`, `lateout(reg)` and `in(reg)` can
share the same register, assuming that the register is written after
all the reads are performed.
It can improve the register allocation.
2. Add `preserves_flags` option as possible.
While RISC-V doesn't have regular condition codes, RISC-V inline
assembly in the Rust language assumes that some registers
(mainly vector state registers) may be overwritten by default.
By adding `preserves_flags` to the intrinsics corresponding
instructions without overwriting such registers, it can minimize
register clobbering on the worst case and adds flexibility to
reorder the instructions.
3. Use trailing semicolon.
As `asm!` declares an action and it doesn't return a value by
itself, it would be better to have trailing semicolon to denote that
an `asm!` call is effectively a statement.
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