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Add f16 inline ASM support for RISC-V
1 parent 92af831 commit 9d45532

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4 files changed

+93
-11
lines changed

4 files changed

+93
-11
lines changed

‎compiler/rustc_codegen_llvm/src/asm.rs‎

Lines changed: 40 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use rustc_codegen_ssa::traits::*;
1313
use rustc_data_structures::fx::FxHashMap;
1414
use rustc_middle::ty::layout::TyAndLayout;
1515
use rustc_middle::{bug, span_bug, ty::Instance};
16-
use rustc_span::{Pos, Span};
16+
use rustc_span::{sym, Pos, Span};
1717
use rustc_target::abi::*;
1818
use rustc_target::asm::*;
1919
use tracing::debug;
@@ -64,7 +64,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
6464
let mut layout = None;
6565
let ty = if let Some(ref place) = place {
6666
layout = Some(&place.layout);
67-
llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout)
67+
llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout, instance)
6868
} else if matches!(
6969
reg.reg_class(),
7070
InlineAsmRegClass::X86(
@@ -112,7 +112,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
112112
// so we just use the type of the input.
113113
&in_value.layout
114114
};
115-
let ty = llvm_fixup_output_type(self.cx, reg.reg_class(), layout);
115+
let ty = llvm_fixup_output_type(self.cx, reg.reg_class(), layout, instance);
116116
output_types.push(ty);
117117
op_idx.insert(idx, constraints.len());
118118
let prefix = if late { "=" } else { "=&" };
@@ -127,8 +127,13 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
127127
for (idx, op) in operands.iter().enumerate() {
128128
match *op {
129129
InlineAsmOperandRef::In { reg, value } => {
130-
let llval =
131-
llvm_fixup_input(self, value.immediate(), reg.reg_class(), &value.layout);
130+
let llval = llvm_fixup_input(
131+
self,
132+
value.immediate(),
133+
reg.reg_class(),
134+
&value.layout,
135+
instance,
136+
);
132137
inputs.push(llval);
133138
op_idx.insert(idx, constraints.len());
134139
constraints.push(reg_to_llvm(reg, Some(&value.layout)));
@@ -139,6 +144,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
139144
in_value.immediate(),
140145
reg.reg_class(),
141146
&in_value.layout,
147+
instance,
142148
);
143149
inputs.push(value);
144150

@@ -341,7 +347,8 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
341347
} else {
342348
self.extract_value(result, op_idx[&idx] as u64)
343349
};
344-
let value = llvm_fixup_output(self, value, reg.reg_class(), &place.layout);
350+
let value =
351+
llvm_fixup_output(self, value, reg.reg_class(), &place.layout, instance);
345352
OperandValue::Immediate(value).store(self, place);
346353
}
347354
}
@@ -919,6 +926,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
919926
mut value: &'ll Value,
920927
reg: InlineAsmRegClass,
921928
layout: &TyAndLayout<'tcx>,
929+
instance: Instance<'_>,
922930
) -> &'ll Value {
923931
let dl = &bx.tcx.data_layout;
924932
match (reg, layout.abi) {
@@ -1029,6 +1037,16 @@ fn llvm_fixup_input<'ll, 'tcx>(
10291037
_ => value,
10301038
}
10311039
}
1040+
(InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1041+
if s.primitive() == Primitive::Float(Float::F16)
1042+
&& !bx.tcx.asm_target_features(instance.def_id()).contains(&sym::zfhmin) =>
1043+
{
1044+
// Smaller floats are always "NaN-boxed" inside larger floats on RISC-V.
1045+
let value = bx.bitcast(value, bx.type_i16());
1046+
let value = bx.zext(value, bx.type_i32());
1047+
let value = bx.or(value, bx.const_u32(0xFFFF_0000));
1048+
bx.bitcast(value, bx.type_f32())
1049+
}
10321050
_ => value,
10331051
}
10341052
}
@@ -1039,6 +1057,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
10391057
mut value: &'ll Value,
10401058
reg: InlineAsmRegClass,
10411059
layout: &TyAndLayout<'tcx>,
1060+
instance: Instance<'_>,
10421061
) -> &'ll Value {
10431062
match (reg, layout.abi) {
10441063
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
@@ -1140,6 +1159,14 @@ fn llvm_fixup_output<'ll, 'tcx>(
11401159
_ => value,
11411160
}
11421161
}
1162+
(InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1163+
if s.primitive() == Primitive::Float(Float::F16)
1164+
&& !bx.tcx.asm_target_features(instance.def_id()).contains(&sym::zfhmin) =>
1165+
{
1166+
let value = bx.bitcast(value, bx.type_i32());
1167+
let value = bx.trunc(value, bx.type_i16());
1168+
bx.bitcast(value, bx.type_f16())
1169+
}
11431170
_ => value,
11441171
}
11451172
}
@@ -1149,6 +1176,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
11491176
cx: &CodegenCx<'ll, 'tcx>,
11501177
reg: InlineAsmRegClass,
11511178
layout: &TyAndLayout<'tcx>,
1179+
instance: Instance<'_>,
11521180
) -> &'ll Type {
11531181
match (reg, layout.abi) {
11541182
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
@@ -1242,6 +1270,12 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12421270
_ => layout.llvm_type(cx),
12431271
}
12441272
}
1273+
(InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1274+
if s.primitive() == Primitive::Float(Float::F16)
1275+
&& !cx.tcx.asm_target_features(instance.def_id()).contains(&sym::zfhmin) =>
1276+
{
1277+
cx.type_f32()
1278+
}
12451279
_ => layout.llvm_type(cx),
12461280
}
12471281
}

‎compiler/rustc_span/src/symbol.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2054,6 +2054,7 @@ symbols! {
20542054
yes,
20552055
yield_expr,
20562056
ymm_reg,
2057+
zfhmin,
20572058
zmm_reg,
20582059
}
20592060
}

‎compiler/rustc_target/src/asm/riscv.rs‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,13 @@ impl RiscVInlineAsmRegClass {
4040
match self {
4141
Self::reg => {
4242
if arch == InlineAsmArch::RiscV64 {
43-
types! { _: I8, I16, I32, I64, F32, F64; }
43+
types! { _: I8, I16, I32, I64, F16, F32, F64; }
4444
} else {
45-
types! { _: I8, I16, I32, F32; }
45+
types! { _: I8, I16, I32, F16, F32; }
4646
}
4747
}
48-
Self::freg => types! { f: F32; d: F64; },
48+
// FIXME(f16_f128): Add `q: F128;` once LLVM support the `Q` extension.
49+
Self::freg => types! { f: F16, F32; d: F64; },
4950
Self::vreg => &[],
5051
}
5152
}

‎tests/assembly/asm/riscv-types.rs‎

Lines changed: 48 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,33 @@
1-
//@ revisions: riscv64 riscv32
1+
//@ revisions: riscv64 riscv32 riscv64-zfhmin riscv32-zfhmin riscv64-zfh riscv32-zfh
22
//@ assembly-output: emit-asm
3+
34
//@[riscv64] compile-flags: --target riscv64imac-unknown-none-elf
45
//@[riscv64] needs-llvm-components: riscv
6+
57
//@[riscv32] compile-flags: --target riscv32imac-unknown-none-elf
68
//@[riscv32] needs-llvm-components: riscv
9+
10+
//@[riscv64-zfhmin] compile-flags: --target riscv64imac-unknown-none-elf --cfg riscv64
11+
//@[riscv64-zfhmin] needs-llvm-components: riscv
12+
//@[riscv64-zfhmin] compile-flags: -C target-feature=+zfhmin
13+
//@[riscv64-zfhmin] filecheck-flags: --check-prefix riscv64
14+
15+
//@[riscv32-zfhmin] compile-flags: --target riscv32imac-unknown-none-elf
16+
//@[riscv32-zfhmin] needs-llvm-components: riscv
17+
//@[riscv32-zfhmin] compile-flags: -C target-feature=+zfhmin
18+
19+
//@[riscv64-zfh] compile-flags: --target riscv64imac-unknown-none-elf --cfg riscv64
20+
//@[riscv64-zfh] needs-llvm-components: riscv
21+
//@[riscv64-zfh] compile-flags: -C target-feature=+zfh
22+
//@[riscv64-zfh] filecheck-flags: --check-prefix riscv64
23+
24+
//@[riscv32-zfh] compile-flags: --target riscv32imac-unknown-none-elf
25+
//@[riscv32-zfh] needs-llvm-components: riscv
26+
//@[riscv32-zfh] compile-flags: -C target-feature=+zfh
27+
728
//@ compile-flags: -C target-feature=+d
829

9-
#![feature(no_core, lang_items, rustc_attrs)]
30+
#![feature(no_core, lang_items, rustc_attrs, f16)]
1031
#![crate_type = "rlib"]
1132
#![no_core]
1233
#![allow(asm_sub_register)]
@@ -33,6 +54,7 @@ type ptr = *mut u8;
3354

3455
impl Copy for i8 {}
3556
impl Copy for i16 {}
57+
impl Copy for f16 {}
3658
impl Copy for i32 {}
3759
impl Copy for f32 {}
3860
impl Copy for i64 {}
@@ -103,6 +125,12 @@ macro_rules! check_reg {
103125
// CHECK: #NO_APP
104126
check!(reg_i8 i8 reg "mv");
105127

128+
// CHECK-LABEL: reg_f16:
129+
// CHECK: #APP
130+
// CHECK: mv {{[a-z0-9]+}}, {{[a-z0-9]+}}
131+
// CHECK: #NO_APP
132+
check!(reg_f16 f16 reg "mv");
133+
106134
// CHECK-LABEL: reg_i16:
107135
// CHECK: #APP
108136
// CHECK: mv {{[a-z0-9]+}}, {{[a-z0-9]+}}
@@ -141,6 +169,12 @@ check!(reg_f64 f64 reg "mv");
141169
// CHECK: #NO_APP
142170
check!(reg_ptr ptr reg "mv");
143171

172+
// CHECK-LABEL: freg_f16:
173+
// CHECK: #APP
174+
// CHECK: fmv.s f{{[a-z0-9]+}}, f{{[a-z0-9]+}}
175+
// CHECK: #NO_APP
176+
check!(freg_f16 f16 freg "fmv.s");
177+
144178
// CHECK-LABEL: freg_f32:
145179
// CHECK: #APP
146180
// CHECK: fmv.s f{{[a-z0-9]+}}, f{{[a-z0-9]+}}
@@ -165,6 +199,12 @@ check_reg!(a0_i8 i8 "a0" "mv");
165199
// CHECK: #NO_APP
166200
check_reg!(a0_i16 i16 "a0" "mv");
167201

202+
// CHECK-LABEL: a0_f16:
203+
// CHECK: #APP
204+
// CHECK: mv a0, a0
205+
// CHECK: #NO_APP
206+
check_reg!(a0_f16 f16 "a0" "mv");
207+
168208
// CHECK-LABEL: a0_i32:
169209
// CHECK: #APP
170210
// CHECK: mv a0, a0
@@ -197,6 +237,12 @@ check_reg!(a0_f64 f64 "a0" "mv");
197237
// CHECK: #NO_APP
198238
check_reg!(a0_ptr ptr "a0" "mv");
199239

240+
// CHECK-LABEL: fa0_f16:
241+
// CHECK: #APP
242+
// CHECK: fmv.s fa0, fa0
243+
// CHECK: #NO_APP
244+
check_reg!(fa0_f16 f16 "fa0" "fmv.s");
245+
200246
// CHECK-LABEL: fa0_f32:
201247
// CHECK: #APP
202248
// CHECK: fmv.s fa0, fa0

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