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Kan LiangIngo Molnar
Kan Liang
authored and
Ingo Molnar
committed
perf/x86/intel: Use the common uarch name for the shared functions
From PMU's perspective, the SPR/GNR server has a similar uarch to the ADL/MTL client p-core. Many functions are shared. However, the shared function name uses the abbreviation of the server product code name, rather than the common uarch code name. Rename these internal shared functions by the common uarch name. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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-34
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3 files changed

+34
-34
lines changed

‎arch/x86/events/intel/core.c‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
299299
EVENT_EXTRA_END
300300
};
301301

302-
static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
302+
static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
303303
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
304304
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
305305
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
@@ -309,7 +309,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
309309
EVENT_EXTRA_END
310310
};
311311

312-
static struct event_constraint intel_spr_event_constraints[] = {
312+
static struct event_constraint intel_glc_event_constraints[] = {
313313
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
314314
FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
315315
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
@@ -349,7 +349,7 @@ static struct event_constraint intel_spr_event_constraints[] = {
349349
EVENT_CONSTRAINT_END
350350
};
351351

352-
static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {
352+
static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
353353
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
354354
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
355355
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
@@ -473,7 +473,7 @@ static u64 intel_pmu_event_map(int hw_event)
473473
return intel_perfmon_event_map[hw_event];
474474
}
475475

476-
static __initconst const u64 spr_hw_cache_event_ids
476+
static __initconst const u64 glc_hw_cache_event_ids
477477
[PERF_COUNT_HW_CACHE_MAX]
478478
[PERF_COUNT_HW_CACHE_OP_MAX]
479479
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
@@ -552,7 +552,7 @@ static __initconst const u64 spr_hw_cache_event_ids
552552
},
553553
};
554554

555-
static __initconst const u64 spr_hw_cache_extra_regs
555+
static __initconst const u64 glc_hw_cache_extra_regs
556556
[PERF_COUNT_HW_CACHE_MAX]
557557
[PERF_COUNT_HW_CACHE_OP_MAX]
558558
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
@@ -4273,7 +4273,7 @@ icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
42734273
}
42744274

42754275
static struct event_constraint *
4276-
spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4276+
glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
42774277
struct perf_event *event)
42784278
{
42794279
struct event_constraint *c;
@@ -4362,7 +4362,7 @@ adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
43624362
struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
43634363

43644364
if (pmu->cpu_type == hybrid_big)
4365-
return spr_get_event_constraints(cpuc, idx, event);
4365+
return glc_get_event_constraints(cpuc, idx, event);
43664366
else if (pmu->cpu_type == hybrid_small)
43674367
return tnt_get_event_constraints(cpuc, idx, event);
43684368

@@ -4409,7 +4409,7 @@ rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
44094409
{
44104410
struct event_constraint *c;
44114411

4412-
c = spr_get_event_constraints(cpuc, idx, event);
4412+
c = glc_get_event_constraints(cpuc, idx, event);
44134413

44144414
/* The Retire Latency is not supported by the fixed counter 0. */
44154415
if (event->attr.precise_ip &&
@@ -4490,7 +4490,7 @@ static void nhm_limit_period(struct perf_event *event, s64 *left)
44904490
*left = max(*left, 32LL);
44914491
}
44924492

4493-
static void spr_limit_period(struct perf_event *event, s64 *left)
4493+
static void glc_limit_period(struct perf_event *event, s64 *left)
44944494
{
44954495
if (event->attr.precise_ip == 3)
44964496
*left = max(*left, 128LL);
@@ -5337,14 +5337,14 @@ static struct attribute *icl_tsx_events_attrs[] = {
53375337
EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
53385338
EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
53395339

5340-
static struct attribute *spr_events_attrs[] = {
5340+
static struct attribute *glc_events_attrs[] = {
53415341
EVENT_PTR(mem_ld_hsw),
53425342
EVENT_PTR(mem_st_spr),
53435343
EVENT_PTR(mem_ld_aux),
53445344
NULL,
53455345
};
53465346

5347-
static struct attribute *spr_td_events_attrs[] = {
5347+
static struct attribute *glc_td_events_attrs[] = {
53485348
EVENT_PTR(slots),
53495349
EVENT_PTR(td_retiring),
53505350
EVENT_PTR(td_bad_spec),
@@ -5357,7 +5357,7 @@ static struct attribute *spr_td_events_attrs[] = {
53575357
NULL,
53585358
};
53595359

5360-
static struct attribute *spr_tsx_events_attrs[] = {
5360+
static struct attribute *glc_tsx_events_attrs[] = {
53615361
EVENT_PTR(tx_start),
53625362
EVENT_PTR(tx_abort),
53635363
EVENT_PTR(tx_commit),
@@ -6215,7 +6215,7 @@ __init int intel_pmu_init(void)
62156215
intel_pmu_pebs_data_source_grt();
62166216
x86_pmu.pebs_latency_data = adl_latency_data_small;
62176217
x86_pmu.get_event_constraints = tnt_get_event_constraints;
6218-
x86_pmu.limit_period = spr_limit_period;
6218+
x86_pmu.limit_period = glc_limit_period;
62196219
td_attr = tnt_events_attrs;
62206220
mem_attr = grt_mem_attrs;
62216221
extra_attr = nhm_format_attr;
@@ -6246,7 +6246,7 @@ __init int intel_pmu_init(void)
62466246
intel_pmu_pebs_data_source_cmt();
62476247
x86_pmu.pebs_latency_data = mtl_latency_data_small;
62486248
x86_pmu.get_event_constraints = cmt_get_event_constraints;
6249-
x86_pmu.limit_period = spr_limit_period;
6249+
x86_pmu.limit_period = glc_limit_period;
62506250
td_attr = cmt_events_attrs;
62516251
mem_attr = grt_mem_attrs;
62526252
extra_attr = cmt_format_attr;
@@ -6563,20 +6563,20 @@ __init int intel_pmu_init(void)
65636563
case INTEL_FAM6_SAPPHIRERAPIDS_X:
65646564
case INTEL_FAM6_EMERALDRAPIDS_X:
65656565
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6566-
x86_pmu.extra_regs = intel_spr_extra_regs;
6566+
x86_pmu.extra_regs = intel_glc_extra_regs;
65676567
fallthrough;
65686568
case INTEL_FAM6_GRANITERAPIDS_X:
65696569
case INTEL_FAM6_GRANITERAPIDS_D:
65706570
pmem = true;
65716571
x86_pmu.late_ack = true;
6572-
memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6573-
memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6572+
memcpy(hw_cache_event_ids, glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6573+
memcpy(hw_cache_extra_regs, glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
65746574

6575-
x86_pmu.event_constraints = intel_spr_event_constraints;
6576-
x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
6575+
x86_pmu.event_constraints = intel_glc_event_constraints;
6576+
x86_pmu.pebs_constraints = intel_glc_pebs_event_constraints;
65776577
if (!x86_pmu.extra_regs)
6578-
x86_pmu.extra_regs = intel_gnr_extra_regs;
6579-
x86_pmu.limit_period = spr_limit_period;
6578+
x86_pmu.extra_regs = intel_rwc_extra_regs;
6579+
x86_pmu.limit_period = glc_limit_period;
65806580
x86_pmu.pebs_ept = 1;
65816581
x86_pmu.pebs_aliases = NULL;
65826582
x86_pmu.pebs_prec_dist = true;
@@ -6586,13 +6586,13 @@ __init int intel_pmu_init(void)
65866586
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
65876587

65886588
x86_pmu.hw_config = hsw_hw_config;
6589-
x86_pmu.get_event_constraints = spr_get_event_constraints;
6589+
x86_pmu.get_event_constraints = glc_get_event_constraints;
65906590
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
65916591
hsw_format_attr : nhm_format_attr;
65926592
extra_skl_attr = skl_format_attr;
6593-
mem_attr = spr_events_attrs;
6594-
td_attr = spr_td_events_attrs;
6595-
tsx_attr = spr_tsx_events_attrs;
6593+
mem_attr = glc_events_attrs;
6594+
td_attr = glc_td_events_attrs;
6595+
tsx_attr = glc_tsx_events_attrs;
65966596
x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
65976597
x86_pmu.lbr_pt_coexist = true;
65986598
intel_pmu_pebs_data_source_skl(pmem);
@@ -6642,7 +6642,7 @@ __init int intel_pmu_init(void)
66426642
x86_pmu.filter = intel_pmu_filter;
66436643
x86_pmu.get_event_constraints = adl_get_event_constraints;
66446644
x86_pmu.hw_config = adl_hw_config;
6645-
x86_pmu.limit_period = spr_limit_period;
6645+
x86_pmu.limit_period = glc_limit_period;
66466646
x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
66476647
/*
66486648
* The rtm_abort_event is used to check whether to enable GPRs
@@ -6691,11 +6691,11 @@ __init int intel_pmu_init(void)
66916691
pmu->intel_cap.perf_metrics = 1;
66926692
pmu->intel_cap.pebs_output_pt_available = 0;
66936693

6694-
memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6695-
memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6696-
pmu->event_constraints = intel_spr_event_constraints;
6697-
pmu->pebs_constraints = intel_spr_pebs_event_constraints;
6698-
pmu->extra_regs = intel_spr_extra_regs;
6694+
memcpy(pmu->hw_cache_event_ids, glc_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6695+
memcpy(pmu->hw_cache_extra_regs, glc_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6696+
pmu->event_constraints = intel_glc_event_constraints;
6697+
pmu->pebs_constraints = intel_glc_pebs_event_constraints;
6698+
pmu->extra_regs = intel_glc_extra_regs;
66996699

67006700
/* Initialize Atom core specific PerfMon capabilities.*/
67016701
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
@@ -6719,7 +6719,7 @@ __init int intel_pmu_init(void)
67196719
pmu->pebs_constraints = intel_grt_pebs_event_constraints;
67206720
pmu->extra_regs = intel_grt_extra_regs;
67216721
if (is_mtl(boot_cpu_data.x86_model)) {
6722-
x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs;
6722+
x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_rwc_extra_regs;
67236723
x86_pmu.pebs_latency_data = mtl_latency_data_small;
67246724
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
67256725
mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;

‎arch/x86/events/intel/ds.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1058,7 +1058,7 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {
10581058
EVENT_CONSTRAINT_END
10591059
};
10601060

1061-
struct event_constraint intel_spr_pebs_event_constraints[] = {
1061+
struct event_constraint intel_glc_pebs_event_constraints[] = {
10621062
INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
10631063
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
10641064

‎arch/x86/events/perf_event.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1521,7 +1521,7 @@ extern struct event_constraint intel_skl_pebs_event_constraints[];
15211521

15221522
extern struct event_constraint intel_icl_pebs_event_constraints[];
15231523

1524-
extern struct event_constraint intel_spr_pebs_event_constraints[];
1524+
extern struct event_constraint intel_glc_pebs_event_constraints[];
15251525

15261526
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
15271527

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