Merge pull-request openvelinux#64 -- 'velinux-kernel-intel/cwf-pmu-6.6' into intel-6.6-velinux

== Description
This is to backport PMU core/uncore/tool upstream patches for CWF platform.

== Test
- core PMU perf counting test
```
[root@cwf linux]# tools/perf/perf stat -a sleep 1
Performance counter stats for 'system wide':

        491,357.35 msec cpu-clock                        #  482.195 CPUs utilized
             2,471      context-switches                 #    5.029 /sec
               481      cpu-migrations                   #    0.979 /sec
                88      page-faults                      #    0.179 /sec
       650,502,887      cycles                           #    0.001 GHz
       185,129,269      instructions                     #    0.28  insn per cycle
        37,198,246      branches                         #   75.705 K/sec
           216,984      branch-misses                    #    0.58% of all branches

       1.019001085 seconds time elapsed
```
- core PMU perf recording tests (fixed and GP counters) pass.
```
[root@cwf linux]# tools/perf/perf record -e instructions -Iax,bx -b -c 100000 sleep 1
[ perf record: Woken up 2 times to write data ]
[ perf record: Captured and wrote 0.047 MB perf.data (27 samples) ]

[root@cwf linux]# tools/perf/perf record -e branches -Iax,bx -b -c 10000 sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.066 MB perf.data (60 samples) ]
```

- uncore devices can be seen in sysfs
```
[root@cwf linux]# ls /sys/devices/* | grep uncore
```

- uncore PMU perf counting tests pass.

```
[root@cwf linux]# tools/perf/perf stat -e uncore_upi/event=0x1/,uncore_cha/event=0x1/,uncore_imc/event=0x1/ -a sleep 1
Performance counter stats for 'system wide':

    25,144,619,084      uncore_upi/event=0x1/
   109,517,186,568      uncore_cha/event=0x1/
    22,178,643,523      uncore_imc/event=0x1/

       1.004042980 seconds time elapsed
```

- CWF specific perf event counting test pass.
```
[root@cwf linux]# tools/perf/perf stat -e LONGEST_LAT_CACHE.MISS,LONGEST_LAT_CACHE.REFERENCE -a sleep 1
Performance counter stats for 'system wide':

           825,684      LONGEST_LAT_CACHE.MISS
        11,596,700      LONGEST_LAT_CACHE.REFERENCE

       1.014799623 seconds time elapsed
```

- CWF specific perf event sampling test pass.
```
[root@cwf linux]# tools/perf/perf record -e LONGEST_LAT_CACHE.MISS,LONGEST_LAT_CACHE.REFERENCE -c 10000 -a sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.852 MB perf.data (1082 samples) ]
```

- GNR TPMI based RAPL PMU events available
```
$ perf list | grep -i energy
      power/energy-pkg/                                  [Kernel PMU event]
      power/energy-ram/                                  [Kernel PMU event]
```

Author: x56Jason

arch/x86/events/amd/core.c

@@ -417,7 +417,7 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 	 * be removed on one CPU at a time AND PMU is disabled
 	 * when we come here
 	 */
-	for (i = 0; i < x86_pmu.num_counters; i++) {
+	for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
 		if (cmpxchg(nb->owners + i, event, NULL) == event)
 			break;
 	}
@@ -484,7 +484,7 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
 	 * because of successive calls to x86_schedule_events() from
 	 * hw_perf_group_sched_in() without hw_perf_enable()
 	 */
-	for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) {
+	for_each_set_bit(idx, c->idxmsk, x86_pmu_max_num_counters(NULL)) {
 		if (new == -1 || hwc->idx == idx)
 			/* assign free slot, prefer hwc->idx */
 			old = cmpxchg(nb->owners + idx, NULL, event);
@@ -527,7 +527,7 @@ static struct amd_nb *amd_alloc_nb(int cpu)
 	/*
 	 * initialize all possible NB constraints
 	 */
-	for (i = 0; i < x86_pmu.num_counters; i++) {
+	for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
 		__set_bit(i, nb->event_constraints[i].idxmsk);
 		nb->event_constraints[i].weight = 1;
 	}
@@ -720,7 +720,7 @@ static void amd_pmu_check_overflow(void)
 	 * counters are always enabled when this function is called and
 	 * ARCH_PERFMON_EVENTSEL_INT is always set.
 	 */
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
 		if (!test_bit(idx, cpuc->active_mask))
 			continue;
 
@@ -740,7 +740,7 @@ static void amd_pmu_enable_all(int added)
 
 	amd_brs_enable_all();
 
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
 		/* only activate events which are marked as active */
 		if (!test_bit(idx, cpuc->active_mask))
 			continue;
@@ -933,7 +933,7 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
 	/* Clear any reserved bits set by buggy microcode */
 	status &= amd_pmu_global_cntr_mask;
 
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
 		if (!test_bit(idx, cpuc->active_mask))
 			continue;
 
@@ -1273,7 +1273,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 	.addr_offset            = amd_pmu_addr_offset,
 	.event_map		= amd_pmu_event_map,
 	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),
-	.num_counters		= AMD64_NUM_COUNTERS,
+	.cntr_mask64		= GENMASK_ULL(AMD64_NUM_COUNTERS - 1, 0),
 	.add			= amd_pmu_add_event,
 	.del			= amd_pmu_del_event,
 	.cntval_bits		= 48,
@@ -1372,7 +1372,7 @@ static int __init amd_core_pmu_init(void)
 	 */
 	x86_pmu.eventsel	= MSR_F15H_PERF_CTL;
 	x86_pmu.perfctr		= MSR_F15H_PERF_CTR;
-	x86_pmu.num_counters	= AMD64_NUM_COUNTERS_CORE;
+	x86_pmu.cntr_mask64	= GENMASK_ULL(AMD64_NUM_COUNTERS_CORE - 1, 0);
 
 	/* Check for Performance Monitoring v2 support */
 	if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) {
@@ -1382,9 +1382,9 @@ static int __init amd_core_pmu_init(void)
 		x86_pmu.version = 2;
 
 		/* Find the number of available Core PMCs */
-		x86_pmu.num_counters = ebx.split.num_core_pmc;
+		x86_pmu.cntr_mask64 = GENMASK_ULL(ebx.split.num_core_pmc - 1, 0);
 
-		amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
+		amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64;
 
 		/* Update PMC handling functions */
 		x86_pmu.enable_all = amd_pmu_v2_enable_all;
@@ -1412,12 +1412,12 @@ static int __init amd_core_pmu_init(void)
 		 * even numbered counter that has a consecutive adjacent odd
 		 * numbered counter following it.
 		 */
-		for (i = 0; i < x86_pmu.num_counters - 1; i += 2)
+		for (i = 0; i < x86_pmu_max_num_counters(NULL) - 1; i += 2)
 			even_ctr_mask |= BIT_ULL(i);
 
 		pair_constraint = (struct event_constraint)
 				    __EVENT_CONSTRAINT(0, even_ctr_mask, 0,
-				    x86_pmu.num_counters / 2, 0,
+				    x86_pmu_max_num_counters(NULL) / 2, 0,
 				    PERF_X86_EVENT_PAIR);
 
 		x86_pmu.get_event_constraints = amd_get_event_constraints_f17h;