From b3ff4afb3154802f4369000f6920edd5dadda2e3 Mon Sep 17 00:00:00 2001 From: audi Date: Tue, 1 Jul 2014 15:25:17 +0800 Subject: [PATCH] QuantaMesh 1000 Series T1048-LB9 ================================================================================ - 1G/10G Datacenter & Enterprise-Class Ethernet switch - 48 10Base-T/100Base-TX/1000Base-T ports - 4 1GbE/10GbE dual speed SFP+ slots - 1 RJ-45 out-of-band management port (10/100/1000M) - 1 RJ-45 console port How to compile ONIE ================================================================================ $ cd onie/machine/quanta/quanta_lb9 $ ./build.sh all How to compile demo installer ================================================================================ $ cd onie/machine/quanta/quanta_lb9 $ ./build.sh demo How to compile documents ================================================================================ $ cd onie/machine/quanta/quanta_lb9 $ ./build.sh docs --- machine/quanta/quanta_lb9/INSTALL | 70 + machine/quanta/quanta_lb9/build.sh | 14 + machine/quanta/quanta_lb9/demo/platform.conf | 5 + machine/quanta/quanta_lb9/kernel/config | 1 + .../quanta_lb9/kernel/pata-port-width.patch | 270 +++ .../kernel/platform-quanta-lb9.patch | 790 +++++++ machine/quanta/quanta_lb9/kernel/series | 3 + machine/quanta/quanta_lb9/machine.make | 23 + machine/quanta/quanta_lb9/onie-rom.conf | 16 + .../u-boot/platform-quanta-lb9.patch | 1891 +++++++++++++++++ machine/quanta/quanta_lb9/u-boot/series | 2 + 11 files changed, 3085 insertions(+) create mode 100755 machine/quanta/quanta_lb9/INSTALL create mode 100755 machine/quanta/quanta_lb9/build.sh create mode 100755 machine/quanta/quanta_lb9/demo/platform.conf create mode 100755 machine/quanta/quanta_lb9/kernel/config create mode 100755 machine/quanta/quanta_lb9/kernel/pata-port-width.patch create mode 100755 machine/quanta/quanta_lb9/kernel/platform-quanta-lb9.patch create mode 100755 machine/quanta/quanta_lb9/kernel/series create mode 100755 machine/quanta/quanta_lb9/machine.make create mode 100755 machine/quanta/quanta_lb9/onie-rom.conf create mode 100755 machine/quanta/quanta_lb9/u-boot/platform-quanta-lb9.patch create mode 100755 machine/quanta/quanta_lb9/u-boot/series diff --git a/machine/quanta/quanta_lb9/INSTALL b/machine/quanta/quanta_lb9/INSTALL new file mode 100755 index 000000000..9d5ef253b --- /dev/null +++ b/machine/quanta/quanta_lb9/INSTALL @@ -0,0 +1,70 @@ +============================= +Installing ONIE on Quanta LB9 +============================= + +Cross-Compiling ONIE +==================== + +Change directories to ``build-config`` to compile ONIE. + +To compile ONIE first change directories to ``build-config`` and then +type ``"make MACHINE=quanta_lb9 all"``. For example:: + + $ cd build-config + $ make -j4 MACHINE=quanta_lb9 all + +When complete, the ONIE binaries are located in +``build/images``:: + + -rw-r--r-- 4849664 May 7 12:06 onie-quanta_lb9-r0.bin + +Installing the ONIE binaries +============================ + +A single binary image needs to be installed on the NOR flash. + +Image 1 -- ONIE kernel and u-boot. + name: onie-quanta_lb9-r0.bin + +Step 1 -- Put the ONIE file on a TFTP server +--------------------------------------------- + +The following directions assume the files are on the root of the TFTP +server. + +Step 2 -- Install image1 (onie-quanta_lb9-r0.bin) +----------------------------------------------- + +Copying the image down using TFTP and flash to the NOR flash:: + + => setenv start 0xffb60000 + => setenv sz.b 0x4a0000 + => tftp onie-quanta_lb9-r0.bin + => protect off $start +${sz.b} && erase $start +${sz.b} + => cp.b $fileaddr $start ${sz.b} && protect on $start +${sz.b} + +Step 3 -- Configure Serial Console +---------------------------------- + +ONIE defaults the serial console baud rate to 115200. You may need to +adjust your terminal settings. + +Step 4 -- Restart The System +---------------------------- + +You can interrupt the boot process by pressing any key during the +count down:: + + => reset + +Step 5 -- Optional +------------------ + +By default the system will start the ONIE in *install* mode. After +booting press the [Enter] key to active the console. + +Alternatively you can start the system in *rescue* mode so you can +login and look around the ONIE. To start the rescue mode type this:: + + => setenv reboot_cmd rescue + => boot diff --git a/machine/quanta/quanta_lb9/build.sh b/machine/quanta/quanta_lb9/build.sh new file mode 100755 index 000000000..4148587ec --- /dev/null +++ b/machine/quanta/quanta_lb9/build.sh @@ -0,0 +1,14 @@ +ONIE_ROOT=$(realpath $(dirname $0)/../../../) +MACHINE=$(basename $(dirname $(realpath $0))) +MACHINEROOT=$ONIE_ROOT/machine/quanta +PARAMS=$* +PARAMS=${PARAMS:-help} +BUILD_IMAGE=$ONIE_ROOT/build/images + +make -C $ONIE_ROOT/build-config MACHINE=$MACHINE MACHINEROOT=$MACHINEROOT $PARAMS + +if [[ $PARAMS =~ .*all.* ]] || [[ $PARAMS =~ .*demo.* ]]; then + echo "Build images path: $BUILD_IMAGE" + ls -l $BUILD_IMAGE/*${MACHINE}* | sed "s#$BUILD_IMAGE/##g" +fi + diff --git a/machine/quanta/quanta_lb9/demo/platform.conf b/machine/quanta/quanta_lb9/demo/platform.conf new file mode 100755 index 000000000..2c7a2705b --- /dev/null +++ b/machine/quanta/quanta_lb9/demo/platform.conf @@ -0,0 +1,5 @@ +# quanta-lb9 specific info + +mtd_dev=/dev/mtd0 +img_start=0xfe000000 +img_sz=0x00400000 diff --git a/machine/quanta/quanta_lb9/kernel/config b/machine/quanta/quanta_lb9/kernel/config new file mode 100755 index 000000000..31006303a --- /dev/null +++ b/machine/quanta/quanta_lb9/kernel/config @@ -0,0 +1 @@ +CONFIG_QUANTA_LB9=y diff --git a/machine/quanta/quanta_lb9/kernel/pata-port-width.patch b/machine/quanta/quanta_lb9/kernel/pata-port-width.patch new file mode 100755 index 000000000..64d809aa5 --- /dev/null +++ b/machine/quanta/quanta_lb9/kernel/pata-port-width.patch @@ -0,0 +1,270 @@ +Support port width and no data swap for OF ata devices + +diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c +index 4cadfa2..50a570c 100644 +--- a/drivers/ata/libata-sff.c ++++ b/drivers/ata/libata-sff.c +@@ -561,12 +561,27 @@ unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 1; ++ unsigned int word; + + /* Transfer multiple of 2 bytes */ +- if (rw == READ) ++ if (rw == READ) { + ioread16_rep(data_addr, buf, words); +- else ++ } else { ++ for (word = 0; word < words; word++) { ++ unsigned char tmp; ++ tmp = buf[word * 2]; ++ buf[word * 2] = buf[word * 2 + 1]; ++ buf[word * 2 + 1] = tmp; ++ } + iowrite16_rep(data_addr, buf, words); ++ } ++ ++ for (word = 0; word < words; word++) { ++ unsigned char tmp; ++ tmp = buf[word * 2]; ++ buf[word * 2] = buf[word * 2 + 1]; ++ buf[word * 2 + 1] = tmp; ++ } + + /* Transfer trailing byte, if any. */ + if (unlikely(buflen & 0x01)) { +@@ -581,9 +596,9 @@ unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, + */ + if (rw == READ) { + ioread16_rep(data_addr, pad, 1); +- *buf = pad[0]; ++ *buf = pad[1]; + } else { +- pad[0] = *buf; ++ pad[1] = *buf; + iowrite16_rep(data_addr, pad, 1); + } + words++; +diff --git a/drivers/ata/pata_of_platform.c b/drivers/ata/pata_of_platform.c +index 2a472c5..7128350 100644 +--- a/drivers/ata/pata_of_platform.c ++++ b/drivers/ata/pata_of_platform.c +@@ -23,9 +23,11 @@ static int __devinit pata_of_platform_probe(struct platform_device *ofdev) + struct resource io_res; + struct resource ctl_res; + struct resource irq_res; +- unsigned int reg_shift = 0; ++ unsigned int port_width = 1; ++ bool port_bswap = 0; + int pio_mode = 0; + int pio_mask; ++ const u32 *reg_shift_prop, *port_width_prop; + const u32 *prop; + + ret = of_address_to_resource(dn, 0, &io_res); +@@ -57,26 +59,31 @@ static int __devinit pata_of_platform_probe(struct platform_device *ofdev) + else + irq_res.flags = 0; + +- prop = of_get_property(dn, "reg-shift", NULL); +- if (prop) +- reg_shift = be32_to_cpup(prop); ++ reg_shift_prop = of_get_property(dn, "reg-shift", NULL); ++ port_width_prop = of_get_property(dn, "port-width", NULL); ++ if (reg_shift_prop && port_width_prop) { ++ dev_err(&ofdev->dev, "invalid configuration, reg-shift and port-width " ++ "are mutually exclusive\n"); ++ return -EINVAL; ++ } ++ ++ if (reg_shift_prop) { ++ unsigned int reg_shift = be32_to_cpup(reg_shift_prop); ++ port_width = (reg_shift ? (reg_shift << 1) : 1); ++ } else if (port_width_prop) { ++ port_width = be32_to_cpup(port_width_prop); ++ } + +- prop = of_get_property(dn, "pio-mode", NULL); ++ prop = of_get_property(dn, "port-bswap", NULL); + if (prop) { +- pio_mode = be32_to_cpup(prop); +- if (pio_mode > 6) { +- dev_err(&ofdev->dev, "invalid pio-mode\n"); +- return -EINVAL; +- } +- } else { +- dev_info(&ofdev->dev, "pio-mode unspecified, assuming PIO0\n"); ++ port_bswap = (be32_to_cpup(prop) != 0); + } + + pio_mask = 1 << pio_mode; + pio_mask |= (1 << pio_mode) - 1; + + return __pata_platform_probe(&ofdev->dev, &io_res, &ctl_res, &irq_res, +- reg_shift, pio_mask); ++ port_width, port_bswap, pio_mask); + } + + static int __devexit pata_of_platform_remove(struct platform_device *ofdev) +diff --git a/drivers/ata/pata_platform.c b/drivers/ata/pata_platform.c +index 2067308..e493501 100644 +--- a/drivers/ata/pata_platform.c ++++ b/drivers/ata/pata_platform.c +@@ -55,20 +55,83 @@ static struct ata_port_operations pata_platform_port_ops = { + .set_mode = pata_platform_set_mode, + }; + ++static void bswap_buf16(unsigned char *buf, unsigned int words) ++{ ++ u16 *wbuf = (u16 *)buf; ++ unsigned int word; ++ ++ for (word = 0; word < words; word++) { ++ *wbuf = (*wbuf << 8) | ((*wbuf >> 8) & 0xff); ++ wbuf++; ++ } ++} ++ ++static unsigned int pata_platform_data_xfer_bswap(struct ata_device *dev, unsigned char *buf, ++ unsigned int buflen, int rw) ++{ ++ struct ata_port *ap = dev->link->ap; ++ void __iomem *data_addr = ap->ioaddr.data_addr; ++ unsigned int words = buflen >> 1; ++ ++ if (ap->pflags & ATA_PFLAG_PIO32) { ++ dev_err(&dev->tdev, "32-bit PIO with port-bswap not impelemented\n"); ++ return 0; ++ } ++ ++ /* Transfer multiple of 2 bytes */ ++ if (rw == READ) { ++ ioread16_rep(data_addr, buf, words); ++ } else { ++ bswap_buf16(buf, words); ++ iowrite16_rep(data_addr, buf, words); ++ } ++ ++ bswap_buf16(buf, words); ++ ++ /* Transfer trailing byte, if any. */ ++ if (unlikely(buflen & 0x01)) { ++ unsigned char pad[2] = { }; ++ ++ /* Point buf to the tail of buffer */ ++ buf += buflen - 1; ++ ++ if (rw == READ) { ++ ioread16_rep(data_addr, pad, 1); ++ *buf = pad[1]; ++ } else { ++ pad[1] = *buf; ++ iowrite16_rep(data_addr, pad, 1); ++ } ++ words++; ++ } ++ ++ return words << 1; ++} ++ + static void pata_platform_setup_port(struct ata_ioports *ioaddr, +- unsigned int shift) ++ unsigned int port_width, ++ bool port_bswap) + { ++ unsigned int port_shift = port_width >> 1; ++ unsigned int data_offset = 0; ++ unsigned int ctl_offset = 0; ++ ++ if (port_bswap) { ++ data_offset = (port_width - 2); ++ ctl_offset = (port_width - 1); ++ } ++ + /* Fixup the port shift for platforms that need it */ +- ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift); +- ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift); +- ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift); +- ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift); +- ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift); +- ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift); +- ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift); +- ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift); +- ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift); +- ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift); ++ ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << port_shift) + data_offset; ++ ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << port_shift) + ctl_offset; ++ ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << port_shift) + ctl_offset; ++ ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << port_shift) + ctl_offset; ++ ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << port_shift) + ctl_offset; ++ ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << port_shift) + ctl_offset; ++ ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << port_shift) + ctl_offset; ++ ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << port_shift) + ctl_offset; ++ ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << port_shift) + ctl_offset; ++ ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << port_shift) + ctl_offset; + } + + /** +@@ -102,7 +165,8 @@ int __devinit __pata_platform_probe(struct device *dev, + struct resource *io_res, + struct resource *ctl_res, + struct resource *irq_res, +- unsigned int ioport_shift, ++ unsigned int port_width, ++ bool port_bswap, + int __pio_mask) + { + struct ata_host *host; +@@ -166,7 +230,12 @@ int __devinit __pata_platform_probe(struct device *dev, + + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; + +- pata_platform_setup_port(&ap->ioaddr, ioport_shift); ++ pata_platform_setup_port(&ap->ioaddr, port_width, port_bswap); ++ if (port_bswap) { ++ pata_platform_port_ops.sff_data_xfer = pata_platform_data_xfer_bswap; ++ } ++ dev_info(dev, "port width: %u byte swap %s\n", ++ port_width, port_bswap ? "enabled" : "disabled"); + + ata_port_desc(ap, "%s cmd 0x%llx ctl 0x%llx", mmio ? "mmio" : "ioport", + (unsigned long long)io_res->start, +@@ -238,7 +307,8 @@ static int __devinit pata_platform_probe(struct platform_device *pdev) + irq_res->flags = pp_info ? pp_info->irq_flags : 0; + + return __pata_platform_probe(&pdev->dev, io_res, ctl_res, irq_res, +- pp_info ? pp_info->ioport_shift : 0, ++ pp_info ? pp_info->port_width : 1, ++ pp_info ? pp_info->port_bswap : false, + pio_mask); + } + +diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h +index 9a26c83..b38ab9c 100644 +--- a/include/linux/ata_platform.h ++++ b/include/linux/ata_platform.h +@@ -7,7 +7,12 @@ struct pata_platform_info { + * constantly spaced and need larger than the 1-byte + * spacing used by ata_std_ports(). + */ +- unsigned int ioport_shift; ++ unsigned int port_width; ++ /* ++ * Handle data byte swapping for platforms with byte-swapped ++ * ports. ++ */ ++ bool port_bswap; + /* + * Indicate platform specific irq types and initial + * IRQ flags when call request_irq() +@@ -19,7 +24,8 @@ extern int __devinit __pata_platform_probe(struct device *dev, + struct resource *io_res, + struct resource *ctl_res, + struct resource *irq_res, +- unsigned int ioport_shift, ++ unsigned int port_width, ++ bool port_bswap, + int __pio_mask); + + extern int __devexit __pata_platform_remove(struct device *dev); diff --git a/machine/quanta/quanta_lb9/kernel/platform-quanta-lb9.patch b/machine/quanta/quanta_lb9/kernel/platform-quanta-lb9.patch new file mode 100755 index 000000000..8c9e03ae1 --- /dev/null +++ b/machine/quanta/quanta_lb9/kernel/platform-quanta-lb9.patch @@ -0,0 +1,790 @@ +Quanta LB9 + +diff --git a/arch/powerpc/boot/dts/quanta_lb9.dts b/arch/powerpc/boot/dts/quanta_lb9.dts +new file mode 100644 +index 0000000..ad7673e +--- /dev/null ++++ b/arch/powerpc/boot/dts/quanta_lb9.dts +@@ -0,0 +1,498 @@ ++/* ++ * Quanta LB9 Device Tree Source ++ * ++ * Copyright 2013 Cumulus Networks, Inc. ++ * Copyright 2006, 2008 Freescale Semiconductor Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ model = "quanta,lb9"; ++ compatible = "quanta,lb9"; ++ reset-gpio = <&cpm_pio_a 24 1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ aliases { ++ ethernet0 = &enet0; ++ ethernet1 = &enet1; ++ serial0 = &serial0; ++ serial1 = &serial1; ++ pci0 = &pci0; ++ pci1 = &pci1; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ PowerPC,8541@0 { ++ device_type = "cpu"; ++ reg = <0x0>; ++ d-cache-line-size = <32>; // 32 bytes ++ i-cache-line-size = <32>; // 32 bytes ++ d-cache-size = <0x8000>; // L1, 32K ++ i-cache-size = <0x8000>; // L1, 32K ++ timebase-frequency = <0>; // 33 MHz, from uboot ++ bus-frequency = <0>; // 166 MHz ++ clock-frequency = <0>; // 825 MHz, from uboot ++ next-level-cache = <&L2>; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ }; ++ ++ bcm_dma { ++ compatible = "early-dma-alloc"; ++ // 64MB DMA region, aligned to 1MB ++ region_size = <0x04000000>; ++ alignment = <0x00100000>; ++ }; ++ ++ mass_storage { ++ device = "sda"; ++ }; ++ ++ soc8541@e0000000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ device_type = "soc"; ++ compatible = "simple-bus"; ++ ranges = <0x0 0xe0000000 0x100000>; ++ bus-frequency = <0>; ++ ++ ecm-law@0 { ++ compatible = "fsl,ecm-law"; ++ reg = <0x0 0x1000>; ++ fsl,num-laws = <8>; ++ }; ++ ++ ecm@1000 { ++ compatible = "fsl,mpc8541-ecm", "fsl,ecm"; ++ reg = <0x1000 0x1000>; ++ interrupts = <17 2>; ++ interrupt-parent = <&mpic>; ++ }; ++ ++ memory-controller@2000 { ++ compatible = "fsl,mpc8541-memory-controller"; ++ reg = <0x2000 0x1000>; ++ interrupt-parent = <&mpic>; ++ interrupts = <18 2>; ++ }; ++ ++ L2: l2-cache-controller@20000 { ++ compatible = "fsl,mpc8541-l2-cache-controller"; ++ reg = <0x20000 0x1000>; ++ cache-line-size = <32>; // 32 bytes ++ cache-size = <0x40000>; // L2, 256K ++ interrupt-parent = <&mpic>; ++ interrupts = <16 2>; ++ }; ++ ++ I2C0: i2c@3000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ cell-index = <0>; ++ compatible = "fsl-i2c"; ++ reg = <0x3000 0x100>; ++ interrupts = <43 2>; ++ interrupt-parent = <&mpic>; ++ dfsrr; ++ ++ rtc@68 { ++ compatible = "dallas,ds1339"; ++ reg = <0x68>; ++ }; ++ ++ board_eeprom@53 { ++ compatible = "at,24c02"; ++ reg = <0x53>; ++ label = "board_eeprom"; ++ }; ++ ++ spd@57 { ++ compatible = ""; ++ reg = <0x57>; ++ }; ++ ++ mux@70 { ++ compatible = "ti,pca9548"; ++ reg = <0x70>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ // 10G SFP+ 0 ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ sfp_eeprom@50 { ++ compatible = "at,24c02"; ++ reg = <0x50>; ++ }; ++ sfp_eeprom@51 { ++ compatible = "at,24c02"; ++ reg = <0x51>; ++ }; ++ }; ++ // 10G SFP+ 1 ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ sfp_eeprom@50 { ++ compatible = "at,24c02"; ++ reg = <0x50>; ++ }; ++ sfp_eeprom@51 { ++ compatible = "at,24c02"; ++ reg = <0x51>; ++ }; ++ }; ++ // 10G SFP+ 2 ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ sfp_eeprom@50 { ++ compatible = "at,24c02"; ++ reg = <0x50>; ++ }; ++ sfp_eeprom@51 { ++ compatible = "at,24c02"; ++ reg = <0x51>; ++ }; ++ }; ++ // 10G SFP+ 3 ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ sfp_eeprom@50 { ++ compatible = "at,24c02"; ++ reg = <0x50>; ++ }; ++ sfp_eeprom@51 { ++ compatible = "at,24c02"; ++ reg = <0x51>; ++ }; ++ }; ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ fancontrol-fb@2C { ++ compatible = "on,adt7470"; ++ reg = <0x2C>; ++ label = "temp fan 1"; ++ }; ++ }; ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ fancontrol-fb@2F { ++ compatible = "on,adt7470"; ++ reg = <0x2F>; ++ label = "temp fan 2"; ++ }; ++ }; ++ }; ++ ++ pca9555@24 { ++ compatible = "nxp,pca9555"; ++ reg = <0x24>; ++ label = "PSU Status 1"; ++ }; ++ pca9555@25 { ++ compatible = "nxp,pca9555"; ++ reg = <0x25>; ++ label = "PSU Status 2"; ++ }; ++ pca9555@20 { ++ compatible = "nxp,pca9555"; ++ reg = <0x20>; ++ label = "8727"; ++ }; ++ }; ++ ++ dma@21300 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; ++ reg = <0x21300 0x4>; ++ ranges = <0x0 0x21100 0x200>; ++ cell-index = <0>; ++ dma-channel@0 { ++ compatible = "fsl,mpc8541-dma-channel", ++ "fsl,eloplus-dma-channel"; ++ reg = <0x0 0x80>; ++ cell-index = <0>; ++ interrupt-parent = <&mpic>; ++ interrupts = <20 2>; ++ }; ++ dma-channel@80 { ++ compatible = "fsl,mpc8541-dma-channel", ++ "fsl,eloplus-dma-channel"; ++ reg = <0x80 0x80>; ++ cell-index = <1>; ++ interrupt-parent = <&mpic>; ++ interrupts = <21 2>; ++ }; ++ dma-channel@100 { ++ compatible = "fsl,mpc8541-dma-channel", ++ "fsl,eloplus-dma-channel"; ++ reg = <0x100 0x80>; ++ cell-index = <2>; ++ interrupt-parent = <&mpic>; ++ interrupts = <22 2>; ++ }; ++ dma-channel@180 { ++ compatible = "fsl,mpc8541-dma-channel", ++ "fsl,eloplus-dma-channel"; ++ reg = <0x180 0x80>; ++ cell-index = <3>; ++ interrupt-parent = <&mpic>; ++ interrupts = <23 2>; ++ }; ++ }; ++ ++ enet0: ethernet@24000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ cell-index = <0>; ++ device_type = "network"; ++ model = "TSEC"; ++ compatible = "gianfar"; ++ reg = <0x24000 0x1000>; ++ ranges = <0x0 0x24000 0x1000>; ++ local-mac-address = [ 00 00 00 00 00 00 ]; ++ interrupts = <29 2 30 2 34 2>; ++ interrupt-parent = <&mpic>; ++ phy-handle = <&phy0>; ++ ++ mdio@520 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "fsl,gianfar-mdio"; ++ reg = <0x520 0x20>; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0x0>; ++ interrupt-parent = <&mpic>; ++ interrupts = <9 1>; ++ device_type = "ethernet-phy"; ++ }; ++ }; ++ }; ++ ++ enet1: ethernet@25000 { ++ status = "disabled"; ++ }; ++ ++ serial0: serial@4500 { ++ cell-index = <0>; ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0x4500 0x100>; ++ clock-frequency = <0>; ++ interrupts = <42 2>; ++ interrupt-parent = <&mpic>; ++ }; ++ ++ serial1: serial@4600 { ++ status = "disabled"; ++ cell-index = <1>; ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0x4600 0x100>; ++ clock-frequency = <0>; ++ interrupts = <42 2>; ++ interrupt-parent = <&mpic>; ++ }; ++ ++ crypto@30000 { ++ compatible = "fsl,sec2.0"; ++ reg = <0x30000 0x10000>; ++ interrupts = <45 2>; ++ interrupt-parent = <&mpic>; ++ fsl,num-channels = <4>; ++ fsl,channel-fifo-len = <24>; ++ fsl,exec-units-mask = <0x7e>; ++ fsl,descriptor-types-mask = <0x01010ebf>; ++ }; ++ ++ mpic: pic@40000 { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ reg = <0x40000 0x40000>; ++ compatible = "chrp,open-pic"; ++ device_type = "open-pic"; ++ }; ++ ++ cpm@919c0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; ++ reg = <0x919c0 0x30>; ++ ranges; ++ ++ muram@80000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x80000 0x10000>; ++ ++ data@0 { ++ compatible = "fsl,cpm-muram-data"; ++ reg = <0x0 0x2000 0x9000 0x1000>; ++ }; ++ }; ++ ++ brg@919f0 { ++ compatible = "fsl,mpc8541-brg", ++ "fsl,cpm2-brg", ++ "fsl,cpm-brg"; ++ reg = <0x919f0 0x10 0x915f0 0x10>; ++ }; ++ ++ cpmpic: pic@90c00 { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ interrupts = <46 2>; ++ interrupt-parent = <&mpic>; ++ reg = <0x90c00 0x80>; ++ compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; ++ }; ++ }; ++ ++ cpm_pio_a: gpio-controller@90d00 { ++ #gpio-cells = <2>; ++ compatible = "fsl,cpm2-pario-bank"; ++ reg = <0x90d00 0x14>; ++ gpio-controller; ++ }; ++ ++ cpm_pio_b: gpio-controller@90d20 { ++ #gpio-cells = <2>; ++ compatible = "fsl,cpm2-pario-bank"; ++ reg = <0x90d20 0x14>; ++ gpio-controller; ++ }; ++ ++ cpm_pio_c: gpio-controller@90d40 { ++ #gpio-cells = <2>; ++ compatible = "fsl,cpm2-pario-bank"; ++ reg = <0x90d40 0x14>; ++ gpio-controller; ++ }; ++ ++ cpm_pio_d: gpio-controller@90d60 { ++ #gpio-cells = <2>; ++ compatible = "fsl,cpm2-pario-bank"; ++ reg = <0x90d60 0x14>; ++ gpio-controller; ++ }; ++ }; ++ ++ pci0: pci@e0008000 { ++ interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; ++ interrupt-map = <0x9000 0x0 0x0 0x1 &mpic 0x3 0x1>; ++ interrupt-parent = <&mpic>; ++ interrupts = <24 2>; ++ bus-range = <0 0>; ++ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 ++ 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; ++ clock-frequency = <66666666>; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ #address-cells = <3>; ++ reg = <0xe0008000 0x1000>; ++ compatible = "fsl,mpc8540-pci"; ++ device_type = "pci"; ++ }; ++ ++ pci1: pci@e0009000 { ++ status = "disabled"; ++ }; ++ ++ localbus@e0005000 { ++ #address-cells = <0x2>; ++ #size-cells = <0x1>; ++ compatible = "fsl,mpc8541-localbus", "fsl,pq2-localbus", "simple-bus"; ++ reg = <0xe0005000 0x1000>; ++ ranges = <0x0 0x0 0xfe000000 0x2000000 ++ 0x1 0x0 0xfc000000 0x2000000 ++ 0x2 0x0 0xf0010000 0x10000 ++ 0x4 0x0 0xf2000000 0x100000 ++ 0x5 0x0 0xf0000000 0x10000>; ++ interrupt-parent = <&mpic>; ++ interrupts = <19 2>; ++ ++ nor@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "cfi-flash"; ++ reg = <0x0 0x0 0x02000000>; ++ bank-width = <2>; ++ partition@0 { ++ /* Entire flash minus (u-boot + onie) */ ++ reg = <0x00000000 0x01b60000>; ++ label = "open"; ++ }; ++ partition@1 { ++ /* 4MB onie */ ++ reg = <0x01b60000 0x00400000>; ++ label = "onie"; ++ }; ++ partition@2 { ++ /* 128KB, 1 sector */ ++ reg = <0x01f60000 0x00020000>; ++ label = "uboot-env"; ++ env_size = <0x2000>; ++ }; ++ partition@3 { ++ /* 512KB u-boot */ ++ reg = <0x01f80000 0x00080000>; ++ label = "uboot"; ++ }; ++ }; ++ ++ nor@1 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "cfi-flash"; ++ reg = <0x1 0x0 0x02000000>; ++ bank-width = <2>; ++ partition@0 { ++ /* Entire 32MB */ ++ reg = <0x00000000 0x02000000>; ++ label = "open2"; ++ }; ++ }; ++ ++ cfcard@1 { ++ compatible = "ata-generic"; ++ device_type = "ide"; ++ reg = <0x5 0x0 0x10000 ++ 0x2 0x0 0x10000>; ++ port-width = <4>; ++ port-bswap; ++ /* XXX - broken at the moment, use poll mode ++ #interrupt-cells = <0x1>; ++ interrupts = <20 2>; ++ interrupt-parent = <&mpic>; ++ */ ++ }; ++ }; ++}; +diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig +index d7946be..cc9e0bd 100644 +--- a/arch/powerpc/platforms/85xx/Kconfig ++++ b/arch/powerpc/platforms/85xx/Kconfig +@@ -222,6 +222,12 @@ config P4080_DS + help + This option enables support for the P4080 DS board + ++config QUANTA_LB9 ++ bool "Quanta Computer LB9" ++ select DEFAULT_UIMAGE ++ help ++ This option enables support for the Quanta Computer LB9 switch platform ++ + endif # PPC32 + + config P5020_DS +diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile +index bc5acb9..68a2a36 100644 +--- a/arch/powerpc/platforms/85xx/Makefile ++++ b/arch/powerpc/platforms/85xx/Makefile +@@ -25,3 +25,4 @@ obj-$(CONFIG_SBC8548) += sbc8548.o + obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o + obj-$(CONFIG_KSI8560) += ksi8560.o + obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o ++obj-$(CONFIG_QUANTA_LB9) += quanta_lb9.o +diff --git a/arch/powerpc/platforms/85xx/quanta_lb9.c b/arch/powerpc/platforms/85xx/quanta_lb9.c +new file mode 100644 +index 0000000..2ceef2b +--- /dev/null ++++ b/arch/powerpc/platforms/85xx/quanta_lb9.c +@@ -0,0 +1,252 @@ ++/* ++ * Quanta LB9 setup and early boot code plus other random bits. ++ * ++ * Copyright 2013 Cumulus Networks, Inc. ++ * Copyright 2005 Freescale Semiconductor Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static unsigned int gpio_reset_handle; ++static bool gpio_reset_valid; ++ ++static int quanta_lb9_find_reset_gpio(unsigned int *handle) ++{ ++ struct device_node *gpio = NULL; ++ struct gpio_chip *gpiochip = NULL; ++ unsigned int gpio_handle = 0; ++ struct device_node *root; ++ enum of_gpio_flags flags; ++ const void *gpio_spec; ++ int rv; ++ ++ root = of_find_node_by_path("/"); ++ rv = of_parse_phandles_with_args(root, "reset-gpio", ++ "#gpio-cells", 0, &gpio, &gpio_spec); ++ if (rv < 0) { ++ printk(KERN_ERR "can't determine reset GPIO from device tree (/reset-gpio)\n"); ++ goto done; ++ } ++ ++ gpiochip = of_node_to_gpiochip(gpio); ++ if (!gpiochip) { ++ printk(KERN_ERR "gpio controller %s isn't registered\n", ++ gpio->full_name); ++ rv = -ENODEV; ++ goto done; ++ } ++ ++ gpio_handle = of_gpio_simple_xlate(gpiochip, root, gpio_spec, &flags); ++ if (gpio_handle < 0) { ++ rv = -ENODEV; ++ goto done; ++ } ++ ++ gpio_handle += gpiochip->base; ++ ++done: ++ if (gpio) { ++ of_node_put(gpio); ++ } ++ if (rv >= 0) { ++ *handle = gpio_handle; ++ } ++ return rv; ++} ++ ++static int __init quanta_lb9_reset_probe(void) ++{ ++ int rv; ++ ++ if (gpio_reset_valid) { ++ return 0; ++ } ++ ++ rv = quanta_lb9_find_reset_gpio(&gpio_reset_handle); ++ if (rv < 0) { ++ printk(KERN_ERR "GPIO reset unavailable\n"); ++ goto done; ++ } ++ ++ ++ rv = gpio_request(gpio_reset_handle, "reset"); ++ if (rv < 0) { ++ printk(KERN_ERR "GPIO reset pin unavailable\n"); ++ goto done; ++ } ++ ++ rv = gpio_direction_output(gpio_reset_handle, 1); ++ if (rv < 0) { ++ printk(KERN_ERR "Unable to set GPIO reset pin direction\n"); ++ goto done; ++ } ++ ++ printk(KERN_INFO "RESET: registered GPIO device: %d\n", gpio_reset_handle); ++ gpio_reset_valid = true; ++ ++done: ++ if (rv < 0) { ++ gpio_free(gpio_reset_handle); ++ gpio_reset_handle = 0; ++ } ++ return rv; ++} ++machine_device_initcall(quanta_lb9, quanta_lb9_reset_probe); ++ ++static void quanta_lb9_restart(char *cmd) ++{ ++ quanta_lb9_reset_probe(); ++ if (gpio_reset_handle) { ++ gpio_set_value(gpio_reset_handle, 0); ++ } else { ++ printk(KERN_ERR "RESET: GPIO not available, power off now.\n"); ++ } ++} ++ ++static void __init quanta_lb9_pic_init(void) ++{ ++ struct mpic *mpic; ++ struct resource r; ++ struct device_node *np = NULL; ++ ++ np = of_find_node_by_type(np, "open-pic"); ++ ++ if (np == NULL) { ++ printk(KERN_ERR "Could not find open-pic node\n"); ++ return; ++ } ++ ++ if (of_address_to_resource(np, 0, &r)) { ++ printk(KERN_ERR "Failed to map mpic register space\n"); ++ of_node_put(np); ++ return; ++ } ++ ++ mpic = mpic_alloc(np, r.start, ++ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, ++ 0, 256, " OpenPIC "); ++ BUG_ON(mpic == NULL); ++ ++ /* Return the mpic node */ ++ of_node_put(np); ++ ++ mpic_init(mpic); ++} ++ ++/* ++ * Setup the architecture ++ */ ++static void __init quanta_lb9_setup_arch(void) ++{ ++#ifdef CONFIG_PCI ++ struct device_node *np; ++#endif ++ ++ if (ppc_md.progress) ++ ppc_md.progress("quanta_lb9_setup_arch()", 0); ++ ++#ifdef CONFIG_PCI ++ for_each_node_by_type(np, "pci") { ++ if (of_device_is_compatible(np, "fsl,mpc8540-pci") || ++ of_device_is_compatible(np, "fsl,mpc8548-pcie")) { ++ struct resource rsrc; ++ of_address_to_resource(np, 0, &rsrc); ++ if ((rsrc.start & 0xfffff) == 0x8000) ++ fsl_add_bridge(np, 1); ++ else ++ fsl_add_bridge(np, 0); ++ } ++ } ++#endif ++} ++ ++static void quanta_lb9_show_cpuinfo(struct seq_file *m) ++{ ++ uint pvid, svid, phid1; ++ ++ pvid = mfspr(SPRN_PVR); ++ svid = mfspr(SPRN_SVR); ++ ++ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); ++ seq_printf(m, "Machine\t\t: Quanta LB9\n"); ++ seq_printf(m, "PVR\t\t: 0x%x\n", pvid); ++ seq_printf(m, "SVR\t\t: 0x%x\n", svid); ++ ++ /* Display cpu Pll setting */ ++ phid1 = mfspr(SPRN_HID1); ++ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); ++} ++ ++/* ++ * Called very early, device-tree isn't unflattened ++ */ ++static int __init quanta_lb9_probe(void) ++{ ++ unsigned long root = of_get_flat_dt_root(); ++ return of_flat_dt_is_compatible(root, "quanta,lb9"); ++} ++ ++static struct of_device_id __initdata of_bus_ids[] = { ++ { .type = "soc", }, ++ { .compatible = "soc", }, ++ { .compatible = "simple-bus", }, ++ { .compatible = "gianfar", }, ++ {}, ++}; ++ ++static int __init declare_of_platform_devices(void) ++{ ++ return of_platform_bus_probe(NULL, of_bus_ids, NULL); ++} ++machine_device_initcall(quanta_lb9, declare_of_platform_devices); ++ ++define_machine(quanta_lb9) { ++ .name = "Quanta LB9", ++ .probe = quanta_lb9_probe, ++ .setup_arch = quanta_lb9_setup_arch, ++ .init_IRQ = quanta_lb9_pic_init, ++ .show_cpuinfo = quanta_lb9_show_cpuinfo, ++ .get_irq = mpic_get_irq, ++ .restart = quanta_lb9_restart, ++ .calibrate_decr = generic_calibrate_decr, ++ .progress = udbg_progress, ++}; diff --git a/machine/quanta/quanta_lb9/kernel/series b/machine/quanta/quanta_lb9/kernel/series new file mode 100755 index 000000000..020451c85 --- /dev/null +++ b/machine/quanta/quanta_lb9/kernel/series @@ -0,0 +1,3 @@ +# This series applies on GIT commit 09301b7d20b369126403ff4c3026edacb5cd9faa +pata-port-width.patch +platform-quanta-lb9.patch diff --git a/machine/quanta/quanta_lb9/machine.make b/machine/quanta/quanta_lb9/machine.make new file mode 100755 index 000000000..56502f363 --- /dev/null +++ b/machine/quanta/quanta_lb9/machine.make @@ -0,0 +1,23 @@ +# Makefile fragment for QUANTA LB9 + +ONIE_ARCH ?= powerpc-softfloat + +VENDOR_REV ?= 0 + +# Translate hardware revision to ONIE hardware revision +ifeq ($(VENDOR_REV),0) + MACHINE_REV = 0 +else + $(warning Unknown VENDOR_REV '$(VENDOR_REV)' for MACHINE '$(MACHINE)') + $(error Unknown VENDOR_REV) +endif + +# Vendor ID -- IANA Private Enterprise Number: +# http://www.iana.org/assignments/enterprise-numbers +VENDOR_ID = 7244 + +#------------------------------------------------------------------------------- +# +# Local Variables: +# mode: makefile-gmake +# End: diff --git a/machine/quanta/quanta_lb9/onie-rom.conf b/machine/quanta/quanta_lb9/onie-rom.conf new file mode 100755 index 000000000..979eba829 --- /dev/null +++ b/machine/quanta/quanta_lb9/onie-rom.conf @@ -0,0 +1,16 @@ +# Quanta LB9 onie ROM configuration + +description="Quanta Computer, LB9" + +# Top Down the NOR flash looks like: +# 1. u-boot image +# 2. u-boot environment +# 3. onie-uimage +format=contiguous + +uboot_machine=QUANTA_LB9 + +# Local Variables: +# mode: shell-script +# eval: (sh-set-shell "/bin/sh" t nil) +# End: diff --git a/machine/quanta/quanta_lb9/u-boot/platform-quanta-lb9.patch b/machine/quanta/quanta_lb9/u-boot/platform-quanta-lb9.patch new file mode 100755 index 000000000..b177e2d3f --- /dev/null +++ b/machine/quanta/quanta_lb9/u-boot/platform-quanta-lb9.patch @@ -0,0 +1,1891 @@ +Quanta LB9 + +diff --git a/board/quanta/quanta_lb9/Makefile b/board/quanta/quanta_lb9/Makefile +new file mode 100644 +index 0000000..657f9cd +--- /dev/null ++++ b/board/quanta/quanta_lb9/Makefile +@@ -0,0 +1,49 @@ ++# ++# Copyright 2004 Freescale Semiconductor. ++# (C) Copyright 2001-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS-y += $(BOARD).o ++COBJS-y += ddr.o ++COBJS-y += law.o ++COBJS-y += tlb.o ++COBJS-y += sys_eeprom.o ++ ++SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS-y)) ++SOBJS := $(addprefix $(obj),$(SOBJS-y)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/quanta/quanta_lb9/ddr.c b/board/quanta/quanta_lb9/ddr.c +new file mode 100644 +index 0000000..78d73b0 +--- /dev/null ++++ b/board/quanta/quanta_lb9/ddr.c +@@ -0,0 +1,56 @@ ++/* ++ * Copyright 2008 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * Version 2 as published by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++void fsl_ddr_board_options(memctl_options_t *popts, ++ dimm_params_t *pdimm, ++ unsigned int ctrl_num) ++{ ++ /* ++ * Factors to consider for clock adjust: ++ * - number of chips on bus ++ * - position of slot ++ * - DDR1 vs. DDR2? ++ * - ??? ++ * ++ * This needs to be determined on a board-by-board basis. ++ * 0110 3/4 cycle late ++ * 0111 7/8 cycle late ++ */ ++ popts->clk_adjust = 6; ++ ++ /* ++ * Factors to consider for CPO: ++ * - frequency ++ * - ddr1 vs. ddr2 ++ */ ++ popts->cpo_override = 0; ++ ++ /* ++ * Factors to consider for write data delay: ++ * - number of DIMMs ++ * ++ * 1 = 1/4 clock delay ++ * 2 = 1/2 clock delay ++ * 3 = 3/4 clock delay ++ * 4 = 1 clock delay ++ * 5 = 5/4 clock delay ++ * 6 = 3/2 clock delay ++ */ ++ popts->write_data_delay = 3; ++ ++ /* ++ * Factors to consider for half-strength driver enable: ++ * - number of DIMMs installed ++ */ ++ popts->half_strength_driver_enable = 0; ++} +diff --git a/board/quanta/quanta_lb9/law.c b/board/quanta/quanta_lb9/law.c +new file mode 100644 +index 0000000..24e0923 +--- /dev/null ++++ b/board/quanta/quanta_lb9/law.c +@@ -0,0 +1,57 @@ ++/* ++ * Copyright 2008 Freescale Semiconductor, Inc. ++ * ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++/* ++ * LAW(Local Access Window) configuration: ++ * ++ * 0x0000_0000 0x7fff_ffff DDR 2G ++ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M ++ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M ++ * 0xe000_0000 0xe000_ffff CCSR 1M ++ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M ++ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M ++ * 0xf000_0000 0xf000_ffff CF CARD 64K ++ * 0xf001_0000 0xf001_ffff CF CARD 64K ++ * 0xfc00_0000 0xfdff_ffff FLASH (2nd bank) 32M ++ * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M ++ * ++ * Notes: ++ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. ++ */ ++ ++struct law_entry law_table[] = { ++ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), ++ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), ++ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_LBC), ++ SET_LAW(CONFIG_SYS_FLASH2_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_LBC), ++ SET_LAW(CONFIG_SYS_CFCARD0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), ++ SET_LAW(CONFIG_SYS_CFCARD1_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), ++}; ++ ++int num_law_entries = ARRAY_SIZE(law_table); +diff --git a/board/quanta/quanta_lb9/quanta_lb9.c b/board/quanta/quanta_lb9/quanta_lb9.c +new file mode 100644 +index 0000000..55c5609 +--- /dev/null ++++ b/board/quanta/quanta_lb9/quanta_lb9.c +@@ -0,0 +1,465 @@ ++/* ++ * Copyright 2004, 2011 Freescale Semiconductor. ++ * ++ * (C) Copyright 2002 Scott McNutt ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) ++extern void ddr_enable_ecc(unsigned int dram_size); ++#endif ++ ++void local_bus_init(void); ++ ++/* ++ * I/O Port configuration table ++ * ++ * if conf is 1, then that port pin will be configured at boot time ++ * according to the five values podr/pdir/ppar/psor/pdat for that entry ++ */ ++const iop_conf_t iop_conf_tab[4][32] = { ++ /* Port A configuration */ ++ { /* conf ppar psor pdir podr pdat */ ++ /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist*/ ++ /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist*/ ++ /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* AD_PWR_GD */ ++ /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* P1V2_PG */ ++ /* PA25 */ { 1, 0, 0, 1, 0, 1 }, /* SOFT_RST_N (Software reset, active low)*/ ++ /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* HARD_RST_N (Hardware reset, active low)*/ ++ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* STATUS_LED (The LED indicate system status, active low)*/ ++ /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA19 */ { 1, 0, 0, 1, 0, 1 }, /* CF_BUS_EN_N (Bus enable for Compact Flash card, active low)*/ ++ /* PA18 */ { 1, 0, 0, 1, 0, 1 }, /* CF_PWR_EN_N (Power enable for Compact Flash card, active low) */ ++ /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* CF_RST_N (Reset Compact Flash card, active low)*/ ++ /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* DMA_RST (Reset CPLD, active low)*/ ++ /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ ++ }, ++ ++ /* Port B configuration */ ++ { /* conf ppar psor pdir podr pdat */ ++ /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PCA9548 Reset, active low. */ ++ /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PHY Reset (BCM5461S), active low. */ ++ /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* All PHY Reset (BCM54680*6+BCM8727*2+BCM5461S), active low. */ ++ /* PB27 */ { 1, 0, 0, 0, 0, 0 }, /* MODULE_INT_N */ ++ /* PB26 */ { 1, 0, 0, 1, 0, 1 }, /* PHY_ISO_N (set all 1G phy to super isolate (active low) */ ++ /* PB25 */ { 1, 0, 0, 1, 0, 1 }, /* MOD_RST_N */ ++ /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB22 */ { 1, 0, 0, 1, 0, 1 }, /* F_RST_N */ ++ /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* MOD_ID_SEL1 */ ++ /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* MOD_ID_SEL0 */ ++ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ ++ }, ++ ++ /* Port C */ ++ { /* conf ppar psor pdir podr pdat */ ++ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* ADT_IRQ_N */ ++ /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* CF_OC_N (Compact Flash card over-current detect active low)*/ ++ /* PC5 */ { 1, 0, 0, 0, 0, 0 }, /* CF_DET1 (Compact Flash card present 1, active low)*/ ++ /* PC4 */ { 1, 0, 0, 0, 0, 0 }, /* CF_DET0 (Compact Flash card present 0, active low)*/ ++ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* RTC_IRQ_N */ ++ }, ++ ++ /* Port D */ ++ { /* conf ppar psor pdir podr pdat */ ++ /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ ++ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ ++ } ++}; ++ ++int ++board_phy_config(struct phy_device *phydev) ++{ ++ struct mii_dev *bus = phydev->bus; ++ unsigned short tmp; ++ ++ /* ++ * Take the management port phy out of isolate mode ++ */ ++ tmp = bus->read(bus, TSEC1_PHYIDX, MDIO_DEVAD_NONE, MII_BMCR); ++ tmp &= ~BMCR_ISOLATE; ++ bus->write(bus, TSEC1_PHYIDX, MDIO_DEVAD_NONE, MII_BMCR, tmp); ++} ++ ++void board_reset(void) ++{ ++ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; ++ volatile ioport_t *iop; ++ ++ iop = ioport_addr(cpm, 0); /* port A */ ++ /* HARD_RST_N */ ++ iop->pdat &= ~0x00000080; ++} ++ ++int ide_preinit(void) ++{ ++ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; ++ volatile ioport_t *iop; ++ ++ iop = ioport_addr(cpm, 2); /* port C */ ++ /* Compact Flash Card Present Signal (Active Low)*/ ++ if (iop->pdat & 0x08000000) { ++ printf ("compact flash not present\n"); ++ return -1; ++ } ++ ++ iop = ioport_addr(cpm, 0); /* port A */ ++ /* Power Enable for Compact Flash Card. */ ++ iop->pdat &= ~0x00002000; ++ ++ iop = ioport_addr(cpm, 0); /* port A */ ++ /* Bus Enable for Compact Flash Card. */ ++ iop->pdat &= ~0x00001000; ++ ++ iop = ioport_addr(cpm, 0); /* port A */ ++ /* Release the Compact Flash Card reset pin. */ ++ iop->pdat |= 0x00004000; ++ ++ return 0; ++} ++ ++int checkboard (void) ++{ ++ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ++ ++ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ ++ ++ printf ("Board: Quanta LB9\n"); ++ ++ printf("PCI1: 32 bit, 66 MHz, %s\n", ++ pci1_clk_sel ? "sync" : "async"); ++ ++ local_bus_init(); ++ ++ return 0; ++} ++ ++/* ++ * Initialize Local Bus ++ */ ++void ++local_bus_init(void) ++{ ++ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; ++ ++ uint clkdiv; ++ uint lbc_hz; ++ sys_info_t sysinfo; ++ uint temp_lbcdll; ++ ++ /* ++ * Errata LBC11. ++ * Fix Local Bus clock glitch when DLL is enabled. ++ * ++ * If localbus freq is < 66MHz, DLL bypass mode must be used. ++ * If localbus freq is > 133MHz, DLL can be safely enabled. ++ * Between 66 and 133, the DLL is enabled with an override workaround. ++ */ ++ ++ get_sys_info(&sysinfo); ++ clkdiv = lbc->lcrr & LCRR_CLKDIV; ++ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; ++ ++ if (lbc_hz < 66) { ++ lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ ++ ++ } else if (lbc_hz >= 133) { ++ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ ++ ++ } else { ++ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ ++ udelay(200); ++ ++ /* ++ * Sample LBC DLL ctrl reg, upshift it to set the ++ * override bits. ++ */ ++ temp_lbcdll = gur->lbcdllcr; ++ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); ++ asm("sync;isync;msync"); ++ } ++} ++ ++#ifdef CONFIG_PCI ++static struct pci_controller hose[] = { ++ {}, ++}; ++#endif /* CONFIG_PCI */ ++ ++void ++pci_init_board(void) ++{ ++#ifdef CONFIG_PCI ++ pci_mpc85xx_init(hose); ++#endif ++} ++ ++#if defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ int node, tmp[2]; ++ const char *path; ++ ++ node = fdt_path_offset(blob, "/aliases"); ++ tmp[0] = 0; ++ if (node >= 0) { ++#ifdef CONFIG_PCI1 ++ path = fdt_getprop(blob, node, "pci0", NULL); ++ if (path) { ++ tmp[1] = hose[0].last_busno - hose[0].first_busno; ++ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); ++ } ++#endif ++#ifdef CONFIG_MPC85XX_PCI2 ++ path = fdt_getprop(blob, node, "pci1", NULL); ++ if (path) { ++ tmp[1] = hose[1].last_busno - hose[1].first_busno; ++ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); ++ } ++#endif ++ } ++} ++ ++static void ft_flash_setup(void *blob, bd_t *bd) ++{ ++ int node; ++ ++ /* ++ * The Quanta LB9 comes in two variants. One variant has a ++ * single 32MB flash part located at CONFIG_SYS_FLASH_BASE. ++ * The other variant has an additional 32MB flash part located ++ * at CONFIG_SYS_FLASH2_BASE. ++ * ++ * If we only have 1 flash part, but a node exists in the ++ * device tree for the 2nd flash part disable it. ++ * ++ * Check if 2nd flash bank is present. If it is not present ++ * disable the corresponding device tree node. ++ * ++ * The check of flash_info[1] below relies on U-Boot's flash ++ * detection. ++ */ ++ if (flash_info[1].flash_id != FLASH_MAN_CFI) { ++ /* ++ * Look for NOR flash node @ CONFIG_SYS_FLASH2_BASE. ++ */ ++ node = fdt_node_offset_by_compat_reg(blob, "cfi-flash", CONFIG_SYS_FLASH2_BASE); ++ if (node >= 0) { ++ fdt_set_node_status(blob, node, FDT_STATUS_DISABLED, 0); ++ } ++ } ++ ++} ++ ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ ft_cpu_setup(blob, bd); ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_flash_setup(blob, bd); ++} ++#endif ++ ++void ide_set_reset(int idereset) ++{ ++ return; ++} ++ ++/******************************************************************************* ++ * ++ * MISC initializations after relocating to RAM. Full C environment available. ++ * Before configuring network interfaces. ++ * ++ * Set the default fan speeds to 40% duty cycle. ++ * ++ */ ++ ++#define HW_MON_I2C_BUS (0) ++#define HW_MON_I2C_MUX_ADDR (0x70) ++ ++enum { ++ ADT7470_PWM1_REG = 0x32, ++ ADT7470_PWM2_REG = 0x33, ++ ADT7470_PWM3_REG = 0x34, ++ ADT7470_PWM4_REG = 0x35, ++}; ++ ++#define ADT7470_1_ADDR (0x2c) ++#define ADT7470_2_ADDR (0x2f) ++ ++int misc_init_r(void) ++{ ++ u8 val; ++ u8 channel[2] = { 4, 5 }; ++ u8 addr[2] = { ADT7470_1_ADDR, ADT7470_2_ADDR }; ++ u8 dev, reg; ++ int bus; ++ u8 pwm_reg[4] = { ++ ADT7470_PWM1_REG, ++ ADT7470_PWM2_REG, ++ ADT7470_PWM3_REG, ++ ADT7470_PWM4_REG, ++ }; ++ ++ bus = i2c_get_bus_num(); ++ i2c_set_bus_num(HW_MON_I2C_BUS); ++ ++ /* ++ * Program all PWM registers on both ADT7470 devices to 40%. ++ */ ++ for (dev = 0; dev < 2; dev++) { ++ /* mux bus-select */ ++ val = 0x1 << channel[dev]; ++ i2c_write(HW_MON_I2C_MUX_ADDR, 0, 1, &val, 1); ++ ++ /* ++ * PWM 0x60 is ~ 40% duty cycle ++ * Write all four PWM registers. ++ */ ++ val = 0x60; ++ for (reg = 0 ; reg < 4; reg++) { ++ i2c_write(addr[dev], pwm_reg[reg], 1, &val, 1); ++ } ++ } ++ ++ /* Disable the MUX */ ++ val = 0; ++ i2c_write(HW_MON_I2C_MUX_ADDR, 0, 1, &val, 1); ++ ++ /* Restore i2c bus */ ++ i2c_set_bus_num(bus); ++ ++ return 0; ++} +diff --git a/board/quanta/quanta_lb9/sys_eeprom.c b/board/quanta/quanta_lb9/sys_eeprom.c +new file mode 100644 +index 0000000..4290766 +--- /dev/null ++++ b/board/quanta/quanta_lb9/sys_eeprom.c +@@ -0,0 +1,576 @@ ++#include ++#include ++#include ++#include ++#include ++ ++#include "sys_eeprom.h" ++ ++/* Convert hex digit to hex character and vice-versa */ ++static int i2xdigit(int digit) ++{ ++ digit &= 0xf; ++ return (digit > 9) ? digit-10+'a' : digit+'0'; ++} ++ ++/* ++ * format_macaddr requires a buffer of 18 bytes minimum. ++ * It does not use sprintf so it can be called from an interrupt context. ++ */ ++static void format_macaddr(char buf[18], char macaddr[6]) ++{ ++ int i; ++ ++ for (i = 0;i <= 5;i++) ++ { ++ *buf++ = i2xdigit(macaddr[i]>>4); ++ *buf++ = i2xdigit(macaddr[i]); ++ *buf++ = ':'; ++ } ++ ++ *--buf = 0; ++} ++ ++#define MAX_DATE_STRING 21 ++/*=======================================================================================*/ ++u8 * versionToString(u32 version) ++{ ++ static u8 verString[MAX_DATE_STRING] ; ++ u32 major, minor/*, build */; ++ ++ major = (version & 0xff000000) >> 24 ; ++ minor = (version & 0x00ff0000) >> 16 ; ++/* build = (version & 0x0000ffff) ;*/ ++ ++/* sprintf(verString, "%02d.%02d.%04d", major, minor, build) ;*/ ++ sprintf(verString, "%d.%d", major, minor) ; ++ ++ return verString ; ++} ++u8 * SoftwareversionToString(u32 version) ++{ ++ static u8 verString[MAX_DATE_STRING] ; ++ u32 major, minor ,v1, v2;/*, build */; ++ ++ major = (version & 0xf0000000) >> 28 ; ++ minor = (version & 0x0f000000) >> 24 ; ++ v1 = (version & 0x00f00000) >> 20 ; ++ v2 = (version & 0x000f0000) >> 16 ; ++ ++/* build = (version & 0x0000ffff) ;*/ ++ ++/* sprintf(verString, "%02d.%02d.%04d", major, minor, build) ;*/ ++ sprintf(verString, "%d.%d.%d.%d", major, minor,v1,v2) ; ++ ++ return verString ; ++} ++/*=======================================================================================*/ ++u8 * dateToString(u32 date) ++{ ++ static u8 dateString[MAX_DATE_STRING] ; ++ u32 year, month, day ; ++ ++ year = (date & 0xffff0000) >> 16 ; ++ month = (date & 0x0000ff00) >> 8 ; ++ day = (date & 0x000000ff) ; ++ ++ sprintf(dateString, "%04d/%d/%d", year, month, day) ; ++ ++ return dateString ; ++} ++/*=======================================================================================*/ ++static int Write_Boardinfo_EEPROM(struct SysBoardInfo *pbdinfo) ++{ ++ u8 writebuffer[EEPROM_24C02_SIZE]; ++ int i , ret=0; ++ ++ memset(writebuffer, 0, EEPROM_24C02_SIZE); ++ memcpy(writebuffer, (u8 *)pbdinfo , SYS_BOARD_INFO_SIZE); ++ ++ for (i=0;iproductName); ++#else ++ printf(" Product Name : %s\r\n", pbdinfo->productName); ++#endif ++ printf(" Model Name : %s\r\n", pbdinfo->modelName); ++ printf(" Serial Number : %s\r\n", pbdinfo->serialNumber); ++ printf(" Part Number : %s\r\n", pbdinfo->partNumber); ++ printf(" Label Revision Number : %s\r\n", pbdinfo->label_revisionNumber); ++ printf(" Hardware Version : %s\r\n", versionToString(pbdinfo->hardwareVersion)); ++#if 1 /* Only show platform number */ ++ printf(" Platform Version : 0x%04x\r\n", pbdinfo->softwareVersion & 0xffff); ++#else ++ printf(" Platform Version : %s (0x%08x)\r\n", SoftwareversionToString(pbdinfo->softwareVersion) , pbdinfo->softwareVersion); ++#endif ++ printf(" Release Date : %s\r\n", dateToString(pbdinfo->releaseDate)); ++ format_macaddr(macString, pbdinfo->macAddr); ++ printf(" MAC Address : %s\r\n", macString); ++} ++/*=======================================================================================*/ ++ ++void BuildBoardInfoDefault (struct SysBoardInfo *boardInfo) ++{ ++ u8 macAddr[6]; ++ u32 a, b, c; ++ ++ memset(boardInfo, 0, sizeof(boardInfo)); ++ ++ strncpy((u8 *)boardInfo->productName, MODEL_NAME, SYS_PRODUCT_NAME_SIZE) ; ++ strncpy((u8 *)boardInfo->partNumber, "123456789", SYS_PART_NUMBER_SIZE) ; ++ strncpy((u8 *)boardInfo->serialNumber, "123456789", SYS_SERIAL_NUMBER_SIZE) ; ++ ++ a = 0; b = 1; c = 0; ++ boardInfo->hardwareVersion = (((a & 0x000000FF) << 24) | ((b & 0x000000FF) << 16) | (c & 0x000000FF)) ; ++ ++ macAddr[0] = 0x00; macAddr[1] = 0xc0; macAddr[2] = 0x9f; ++ macAddr[3] = 0x01; macAddr[4] = 0x02; macAddr[5] = 0x03; ++ memcpy(boardInfo->macAddr, macAddr, 6) ; ++ ++ boardInfo->softwareVersion = CONFIG_QUANTA_SOFT_VERSION; ++ ++ strncpy((u8 *)boardInfo->label_revisionNumber, "1", SYS_LABEL_REVISION_NUMBER_SIZE) ; ++ a = 2012; b = 1; c = 1; ++ boardInfo->releaseDate = (((a & 0x0000FFFF) << 16) | ((b & 0x000000FF) << 8) | (c & 0x000000FF)) ; ++ strncpy((u8 *)boardInfo->modelName, "QUANTA "MODEL_NAME, SYS_MODEL_NAME_SIZE) ; ++ ++ boardInfo->checksum = crc32(0,boardInfo, SYS_BOARD_INFO_SIZE - sizeof(unsigned int)) ; ++ ++ printf("\nUpdating board information by default, please wait ... "); ++#if 0 ++ if (Write_Boardinfo_EEPROM(boardInfo)==0) ++ printf(" Done.\n"); ++ else ++ printf(" FAIL.\n"); ++#else ++ printf(" NOT!\n"); ++#endif ++} ++/*=======================================================================================*/ ++ ++void BuildEEPROMData(struct SysBoardInfo *pbdinfo) ++{ ++ unsigned short total_zize, str_length; ++ unsigned int CradTypeNum; ++ unsigned short computed_crc; ++ unsigned char writebuffer[EEPROM_24C02_SIZE]; ++ u32 a, b, c; ++ char macAddr[6]; ++ ++ memset(pbdinfo, 0, SYS_BOARD_INFO_SIZE); ++ ++ strncpy((u8 *)pbdinfo->productName, MODEL_NAME, SYS_PRODUCT_NAME_SIZE) ; ++ ++ strncpy((char *)pbdinfo->partNumber, "123456789", SYS_PART_NUMBER_SIZE) ; ++ strncpy((char *)pbdinfo->serialNumber, "123456789", SYS_SERIAL_NUMBER_SIZE) ; ++ a = 0; b = 1; c = 0; ++ pbdinfo->hardwareVersion = (((a & 0x000000FF) << 24) | ((b & 0x000000FF) << 16) | (c & 0x000000FF)) ; ++ macAddr[0] = 0x00; macAddr[1] = 0xc0; macAddr[2] = 0x9f; ++ macAddr[3] = 0x01; macAddr[4] = 0x02; macAddr[5] = 0x03; ++ memcpy(pbdinfo->macAddr, macAddr, 6) ; ++ ++ pbdinfo->softwareVersion = CONFIG_QUANTA_SOFT_VERSION; ++ ++ strncpy((char *)pbdinfo->label_revisionNumber, "1", SYS_LABEL_REVISION_NUMBER_SIZE) ; ++ a = 2012; b = 1; c = 1; ++ pbdinfo->releaseDate = (((a & 0x0000FFFF) << 16) | ((b & 0x000000FF) << 8) | (c & 0x000000FF)) ; ++ ++ strncpy((u8 *)pbdinfo->modelName, "QUANTA "MODEL_NAME, SYS_MODEL_NAME_SIZE) ; ++ ++ /* pbdinfo->checksum = crc32(0,pbdinfo, SYS_BOARD_INFO_SIZE - sizeof(unsigned int)) ;*/ ++ ++ memset(writebuffer, 0, EEPROM_24C02_SIZE); ++ total_zize = 0; ++ ++ /* Magic Number */ ++ writebuffer[total_zize++] = EEPROM_Type_Magic_Num; ++ writebuffer[total_zize++] = EEPROM_Magic_Num_Length; ++ writebuffer[total_zize++] = EEPROM_Magic_Num; ++ ++ /* Product Name */ ++ str_length = strlen((char *)pbdinfo->productName); ++ if ((str_length>0)&&(str_length<=EEPROM_Max_Product_Name_Length)) ++ { ++ writebuffer[total_zize++] = EEPROM_Type_Product_Name; ++ writebuffer[total_zize++] = str_length; ++ memcpy(&writebuffer[total_zize], pbdinfo->productName, str_length); ++ total_zize += str_length; ++ } ++ ++ /* Part Number */ ++ str_length = strlen((char *)pbdinfo->partNumber); ++ if ((str_length>0)&&(str_length<=EEPROM_Max_Part_Length)) ++ { ++ writebuffer[total_zize++] = EEPROM_Type_Part; ++ writebuffer[total_zize++] = str_length; ++ memcpy(&writebuffer[total_zize], pbdinfo->partNumber, str_length); ++ total_zize += str_length; ++ } ++ ++ /* Serial Number */ ++ str_length = strlen((char *)pbdinfo->serialNumber); ++ if ((str_length>0)&&(str_length<=EEPROM_Max_Serial_Length)) ++ { ++ writebuffer[total_zize++] = EEPROM_Type_Serial; ++ writebuffer[total_zize++] = str_length; ++ memcpy(&writebuffer[total_zize], pbdinfo->serialNumber, str_length); ++ total_zize += str_length; ++ } ++ ++ /* MAC Address */ ++ writebuffer[total_zize++] = EEPROM_Type_MAC; ++ writebuffer[total_zize++] = EEPROM_MAC_Length; ++ memcpy(&writebuffer[total_zize], pbdinfo->macAddr, EEPROM_MAC_Length); ++ total_zize += EEPROM_MAC_Length; ++ ++ /* Date of Manufacture */ ++ writebuffer[total_zize++] = EEPROM_Type_Date; ++ writebuffer[total_zize++] = EEPROM_Date_Length; ++ memcpy(&writebuffer[total_zize], (unsigned char *)&pbdinfo->releaseDate, EEPROM_Date_Length); ++ total_zize += EEPROM_Date_Length; ++ ++ /* Card Type */ ++ CradTypeNum = EEPROM_Card_Type; ++ writebuffer[total_zize++] = EEPROM_Type_Card_Type; ++ writebuffer[total_zize++] = EEPROM_Card_Type_Length; ++ memcpy(&writebuffer[total_zize], (unsigned char *)&CradTypeNum, EEPROM_Card_Type_Length); ++ total_zize += EEPROM_Card_Type_Length; ++ ++ /* Hardware Revision */ ++ writebuffer[total_zize++] = EEPROM_Type_Hardware_Version; ++ writebuffer[total_zize++] = EEPROM_Hardware_Version_Length; ++ memcpy(&writebuffer[total_zize], (unsigned char *)&pbdinfo->hardwareVersion, EEPROM_Hardware_Version_Length); ++ total_zize += EEPROM_Hardware_Version_Length; ++ ++ /* Label Revision Number */ ++ str_length = strlen((char *)pbdinfo->label_revisionNumber); ++ if ((str_length>0)&&(str_length<=EEPROM_Max_Label_Revision_Length)) ++ { ++ writebuffer[total_zize++] = EEPROM_Type_Label_Revision; ++ writebuffer[total_zize++] = str_length; ++ memcpy(&writebuffer[total_zize], pbdinfo->label_revisionNumber, str_length); ++ total_zize += str_length; ++ } ++ ++ /* Model Name */ ++ str_length = strlen((char *)pbdinfo->modelName); ++ if ((str_length>0)&&(str_length<=EEPROM_Max_Model_Name_Length)) ++ { ++ writebuffer[total_zize++] = EEPROM_Type_Model_Name; ++ writebuffer[total_zize++] = str_length; ++ memcpy(&writebuffer[total_zize], pbdinfo->modelName, str_length); ++ total_zize += str_length; ++ } ++ ++ /* Software Revision */ ++ writebuffer[total_zize++] = EEPROM_Type_Software_Version; ++ writebuffer[total_zize++] = EEPROM_Software_Version_Length; ++ memcpy(&writebuffer[total_zize], (unsigned char *)&pbdinfo->softwareVersion, EEPROM_Software_Version_Length); ++ total_zize += EEPROM_Software_Version_Length; ++ ++ /* CRC16-CCITT */ ++ writebuffer[total_zize++] = EEPROM_Type_CRC16; ++ writebuffer[total_zize++] = EEPROM_CRC16_Length; ++ ++#if 0 ++ CRC_Init(); ++ computed_crc = (UI16)crcbitbybit(writebuffer, total_zize); ++#else ++ computed_crc = 0; ++ computed_crc = crc32(computed_crc, writebuffer, total_zize); ++#endif ++ writebuffer[total_zize++] = (computed_crc&0xff); ++ writebuffer[total_zize++] = (computed_crc>>8)&0xff; ++ ++ printf("\nUpdating board information by default, please wait ... "); ++#if 0 ++ if (Write_Boardinfo_EEPROM(writebuffer)==0) ++ printf(" Done.\n"); ++ else ++ printf(" FAIL.\n"); ++#else ++ printf(" NOT!\n"); ++#endif ++ ++ return; ++} ++ ++int ReadEEPROMData(struct SysBoardInfo *pbdinfo, unsigned char *Readbuffer) ++{ ++ unsigned short idx, str_length, type; ++ unsigned short computed_crc, read_crc; ++ char magic_number_flag, crc_number_flag; ++ ++ magic_number_flag = crc_number_flag = 0; ++ idx = 0; ++ while (1) ++ { ++ type = Readbuffer[idx++]; ++ str_length = Readbuffer[idx++]; ++ if (str_length>0) ++ { ++ switch(type) ++ { ++ /* Check Magic Number */ ++ case EEPROM_Type_Magic_Num: ++ if (Readbuffer[idx] == EEPROM_Magic_Num) ++ magic_number_flag = 1; ++ break; ++ ++ /* Read Product Name */ ++ case EEPROM_Type_Product_Name: ++ memcpy(pbdinfo->productName, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Model Name */ ++ case EEPROM_Type_Model_Name: ++ memcpy(pbdinfo->modelName, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Part Number */ ++ case EEPROM_Type_Part: ++ memcpy(pbdinfo->partNumber, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Serial Number */ ++ case EEPROM_Type_Serial: ++ memcpy(pbdinfo->serialNumber, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Label Revision Number */ ++ case EEPROM_Type_Label_Revision: ++ memcpy(pbdinfo->label_revisionNumber, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read MAC Address */ ++ case EEPROM_Type_MAC: ++ memcpy(pbdinfo->macAddr, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Hardware Revision */ ++ case EEPROM_Type_Hardware_Version: ++ memcpy(&pbdinfo->hardwareVersion, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Software Revision */ ++ case EEPROM_Type_Software_Version: ++ memcpy(&pbdinfo->softwareVersion, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Read Release Date*/ ++ case EEPROM_Type_Date: ++ memcpy(&pbdinfo->releaseDate, &Readbuffer[idx], str_length); ++ break; ++ ++ /* Check CRC16-CCITT */ ++ case EEPROM_Type_CRC16: ++ computed_crc = read_crc = 0; ++ read_crc = Readbuffer[idx] + (Readbuffer[idx+1]<<8); ++ computed_crc = crc32(computed_crc, Readbuffer, idx); ++ if (read_crc==computed_crc) ++ crc_number_flag = 1; ++ break; ++ } ++ idx += str_length; ++ } ++ if (idx>(EEPROM_24C02_SIZE-5)) break; ++ } ++ ++ if ((magic_number_flag)&&(crc_number_flag)) ++ return 1; ++ ++ printf("EEPROM data error (computed_crc(%#08x) != read_crc(%#08x)) , \r\nCan't read MAC address from EEPROM!!\r\n" ,computed_crc , read_crc); ++ return 0; ++} ++ ++static struct SysBoardInfo g_pbdinfo; ++static int info_read = 0; ++ ++static int PopulateBoardData(void) ++{ ++ char dataBuffer[EEPROM_24C02_SIZE]; ++ int i; ++ unsigned int chksum = 0; ++ int rc = 0; ++ ++ if (info_read) ++ return 0; ++ ++ memset(dataBuffer, 0, sizeof(dataBuffer)); ++ ++#if defined(CONFIG_LY2_P2020) || defined(CONFIG_LY3_P2020) /* Add By Arius ---- 09/13/2011 */ ++ char data = 0x01; ++ /* Do Channel Select */ ++ if (i2c_write(I2C_PCA9546_FAN_I2C_SWITCH, 0x00, 1, &data, 1 ) != 0) ++ { ++ puts("I2C error ! Can't select Channel for PCA9546A!!\r\n"); ++ return 1; ++ } ++#endif ++ ++#if 1 /*using Type/Length/Data format*/ ++ memset(dataBuffer, 0, sizeof(dataBuffer)); ++ memset(&g_pbdinfo, 0, SYS_BOARD_INFO_SIZE); ++ ++ i2c_set_bus_num(0); ++ ++#if defined(CONFIG_SB1A_P1010) || defined(CONFIG_SB1B_P1010) ++ if (i2c_read(I2C_AT24C02_EEPROM_MB, 0x00, 2, dataBuffer, EEPROM_24C02_SIZE) == 0) ++#else ++ if (i2c_read(I2C_AT24C02_EEPROM_MB, 0x00, 1, dataBuffer, EEPROM_24C02_SIZE) == 0) ++#endif ++ { ++ if (ReadEEPROMData(&g_pbdinfo, dataBuffer)) ++ { ++ ShowBoardInfo(&g_pbdinfo); ++ } ++ else ++ { ++ puts("Error parsing TLV EEPROM data :"); ++ rc = 1; ++ for(i = 0; i < EEPROM_24C02_SIZE; i++) ++ { ++ if ((i % 16) == 0) printf("\r\n"); ++ printf(" %02x", dataBuffer[i]); ++ } ++ BuildEEPROMData(&g_pbdinfo); ++ ShowBoardInfo(&g_pbdinfo); ++ } ++ } ++ else ++ { ++ puts("I2C error ! Can't read EEPROM data!!\r\n"); ++ rc = 1; ++ BuildEEPROMData(&g_pbdinfo); ++ ShowBoardInfo(&g_pbdinfo); ++ } ++#else ++ if (i2c_read(I2C_AT24C02_EEPROM_MB, 0x00, 1, dataBuffer, EEPROM_24C02_SIZE ) == 0) ++ { ++ memcpy(&g_pbdinfo, dataBuffer, sizeof(struct SysBoardInfo)); ++ chksum = crc32(0, (unsigned char *)&g_pbdinfo, SYS_BOARD_INFO_SIZE - sizeof(unsigned int)) ; ++ ++ if (g_pbdinfo.checksum == chksum) ++ { ++ ShowBoardInfo(&g_pbdinfo); ++ } ++ else ++ { ++ printf("EEPROM data error (checksum(%#08x) != pbdinfo.checksum(%#08x)) , \r\n" ++ "Can't read MAC address from EEPROM!!\r\n" , chksum , g_pbdinfo.checksum); ++ rc = 1; ++ puts("EEPROM data :"); ++ for(i = 0; i < EEPROM_24C02_SIZE; i++) ++ { ++ if ((i % 16) == 0) printf("\r\n"); ++ printf(" %02x", dataBuffer[i]); ++ } ++ BuildBoardInfoDefault(&g_pbdinfo); ++ ShowBoardInfo(&g_pbdinfo); ++ } ++ } ++ else ++ { ++ puts("I2C error ! Can't read EEPROM data!!\r\n"); ++ rc = 1; ++ BuildBoardInfoDefault(&g_pbdinfo); ++ ShowBoardInfo(&g_pbdinfo); ++ } ++#endif ++ ++ softwareVersion = g_pbdinfo.softwareVersion; ++ ++#if defined(CONFIG_LY2_P2020) || defined(CONFIG_LY3_P2020) /* Add By Arius ---- 09/13/2011 */ ++ /* Do Channel Release */ ++ data = 0x00; ++ if (i2c_write(I2C_PCA9546_FAN_I2C_SWITCH, 0x00, 1, &data, 1 ) != 0) ++ { ++ puts("I2C error ! Can't Release Channel for PCA9546A!!\r\n"); ++ rc = 1; ++ } ++#endif ++ ++ info_read = 1; ++ return rc; ++} ++ ++/** ++ * mac_read_from_eeprom ++ * ++ * Read the MAC addresses from EEPROM ++ * ++ * This function reads the MAC addresses from EEPROM and sets the ++ * appropriate environment variables for each one read. ++ * ++ * The environment variables are only set if they haven't been set already. ++ * This ensures that any user-saved variables are never overwritten. ++ * ++ * This function must be called after relocation. ++ */ ++int mac_read_from_eeprom(void) ++{ ++ char macString[18]; ++ ++ if (PopulateBoardData() == 0) { ++ if (getenv("ethaddr")) ++ return 0; ++ ++ format_macaddr(macString, (char *)g_pbdinfo.macAddr); ++ setenv ("ethaddr", macString); ++ } else { ++ printf("Reading EEPROM failed.\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_POPULATE_SERIAL_NUMBER ++/** ++ * populate_serial_number - read the serial number from EEPROM ++ * ++ * This function reads the serial number from the EEPROM and sets the ++ * appropriate environment variable. ++ * ++ * The environment variable is only set if it has not been set ++ * already. This ensures that any user-saved variables are never ++ * overwritten. ++ * ++ * This function must be called after relocation. ++ */ ++int populate_serial_number(void) ++{ ++ ++ if (PopulateBoardData() == 0) { ++ if (getenv("serial#")) ++ return 0; ++ ++ g_pbdinfo.serialNumber[SYS_SERIAL_NUMBER_SIZE - 1] = '\0'; ++ setenv ("serial#", (char *)g_pbdinfo.serialNumber); ++ } else { ++ printf("Reading EEPROM failed.\n"); ++ return 1; ++ } ++ ++ return 0; ++} ++#endif /* CONFIG_POPULATE_SERIAL_NUMBER */ +diff --git a/board/quanta/quanta_lb9/sys_eeprom.h b/board/quanta/quanta_lb9/sys_eeprom.h +new file mode 100644 +index 0000000..f738bc1 +--- /dev/null ++++ b/board/quanta/quanta_lb9/sys_eeprom.h +@@ -0,0 +1,77 @@ ++#ifndef __SYS_EEPROM_H_ ++#define __SYS_EEPROM_H_ ++ ++/* ++ * Board information definitions ++ */ ++#define SYS_BOARD_INFO_SIZE 160 /* board info size */ ++#define SYS_PRODUCT_NAME_SIZE 32 /* max. product name size */ ++#define SYS_MODEL_NAME_SIZE 20 /* max. model name size */ ++#define SYS_PART_NUMBER_SIZE 20 /* max. part number size */ ++#define SYS_SERIAL_NUMBER_SIZE 20 /* max. serial number size */ ++#define SYS_LABEL_REVISION_NUMBER_SIZE 20 /* max. label reversion number size */ ++#define SYS_MAC_ADDR_SIZE 6 /* mac address size */ ++ ++#define XMK_STR(x) #x ++#define MK_STR(x) XMK_STR(x) ++ ++struct SysBoardInfo { ++ u8 productName[SYS_PRODUCT_NAME_SIZE]; /* product name */ ++ u8 modelName[SYS_MODEL_NAME_SIZE]; /* model name */ ++ u8 partNumber[SYS_PART_NUMBER_SIZE]; /* part number */ ++ u8 serialNumber[SYS_SERIAL_NUMBER_SIZE]; /* serial number */ ++ u8 label_revisionNumber[SYS_LABEL_REVISION_NUMBER_SIZE]; /* label revision serial number */ ++ u32 hardwareVersion ; /* hardware version of this board ++ * B1: major version, B2: minor version, ++ * B3: test stage, eg. A, B, C..., R for release, ++ * B4: test minor version ++ * eg. 1.03B1 for version 1.03 B Test 1 ++ */ ++ u32 softwareVersion ; /* software version of this board ++ * B1: major version, B2: minor version, ++ * B3: test stage, eg. A, B, C..., R for release, ++ * B4: test minor version ++ * eg. 1.03B1 for version 1.03 B Test 1 ++ */ ++ u32 releaseDate ; /* release date */ ++ u8 macAddr[SYS_MAC_ADDR_SIZE] ; /* mac address */ ++ u8 Manufacture_Mode ; /* 0 : Normal 1 : Auto in Diagnostic Test Mode 2 : Auto in Burn-In test Mode */ ++ u8 reserved[25] ; /* reserved, should be all zero! */ ++ u32 checksum ; /* checksum of BoardInfo except this field */ ++} ; ++ ++ ++unsigned long softwareVersion ; /* software version of this board*/ ++ ++ ++#define String_Type_Length 20 ++#define EEPROM_Type_Magic_Num 0xFF ++#define EEPROM_Type_Product_Name 0x01 ++#define EEPROM_Type_Part 0x02 ++#define EEPROM_Type_Serial 0x03 ++#define EEPROM_Type_MAC 0x04 ++#define EEPROM_Type_Date 0x05 ++#define EEPROM_Type_Card_Type 0x06 ++#define EEPROM_Type_Hardware_Version 0x07 ++#define EEPROM_Type_Label_Revision 0x08 ++#define EEPROM_Type_Model_Name 0x09 ++#define EEPROM_Type_Software_Version 0x0A ++#define EEPROM_Type_CRC16 0x00 ++ ++#define EEPROM_Magic_Num_Length 1 ++#define EEPROM_Max_Product_Name_Length SYS_PRODUCT_NAME_SIZE ++#define EEPROM_Max_Part_Length SYS_PART_NUMBER_SIZE ++#define EEPROM_Max_Serial_Length SYS_SERIAL_NUMBER_SIZE ++#define EEPROM_MAC_Length SYS_MAC_ADDR_SIZE ++#define EEPROM_Max_Label_Revision_Length SYS_LABEL_REVISION_NUMBER_SIZE ++#define EEPROM_Max_Model_Name_Length SYS_MODEL_NAME_SIZE ++#define EEPROM_Date_Length 4 ++#define EEPROM_Card_Type_Length 4 ++#define EEPROM_Hardware_Version_Length 4 ++#define EEPROM_Software_Version_Length 4 ++#define EEPROM_CRC16_Length 2 ++ ++#define EEPROM_Magic_Num 0xE0 ++#define EEPROM_Card_Type 0x00000001 ++ ++#endif +diff --git a/board/quanta/quanta_lb9/tlb.c b/board/quanta/quanta_lb9/tlb.c +new file mode 100644 +index 0000000..2c5a054 +--- /dev/null ++++ b/board/quanta/quanta_lb9/tlb.c +@@ -0,0 +1,88 @@ ++/* ++ * Copyright 2008 Freescale Semiconductor, Inc. ++ * ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++struct fsl_e_tlb_entry tlb_table[] = { ++ /* TLB 0 - for temp stack in cache */ ++ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, ++ MAS3_SX|MAS3_SW|MAS3_SR, 0, ++ 0, 0, BOOKE_PAGESZ_4K, 0), ++ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, ++ MAS3_SX|MAS3_SW|MAS3_SR, 0, ++ 0, 0, BOOKE_PAGESZ_4K, 0), ++ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, ++ MAS3_SX|MAS3_SW|MAS3_SR, 0, ++ 0, 0, BOOKE_PAGESZ_4K, 0), ++ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, ++ MAS3_SX|MAS3_SW|MAS3_SR, 0, ++ 0, 0, BOOKE_PAGESZ_4K, 0), ++ ++ /* ++ * CCSRBAR: Non-cacheable, guarded ++ * 0xe000_0000 1M CCSRBAR ++ */ ++ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, ++ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, ++ 0, 0, BOOKE_PAGESZ_1M, 1), ++ ++ /* ++ * FLASH: Non-cacheable, guarded ++ * 0xfc000000 32M 2nd Flash ++ * 0xfe000000 32M Boot Flash ++ * Out of reset this entry is only 4K. ++ */ ++ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH2_BASE, CONFIG_SYS_FLASH2_BASE_PHYS, ++ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, ++ 0, 1, BOOKE_PAGESZ_64M, 1), ++ ++ /* ++ * PCI1 MEM First Half ++ * 0x80000000 256M Non-cacheable, guarded ++ */ ++ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, ++ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, ++ 0, 2, BOOKE_PAGESZ_256M, 1), ++ ++ /* ++ * PCI1 MEM Second Half ++ * 0x90000000 256M Non-cacheable, guarded ++ */ ++ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, ++ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, ++ 0, 3, BOOKE_PAGESZ_256M, 1), ++ ++ /* ++ * CF Card: Non-cacheable, guarded ++ * 0xf0000000 64K Control Registers ++ * 0xf0010000 64K Alt Registers ++ */ ++ SET_TLB_ENTRY(1, CONFIG_SYS_CFCARD0_BASE, CONFIG_SYS_CFCARD0_BASE_PHYS, ++ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, ++ 0, 4, BOOKE_PAGESZ_64K, 1), ++}; ++ ++int num_tlb_entries = ARRAY_SIZE(tlb_table); +diff --git a/boards.cfg b/boards.cfg +index e4b0d44..27ada52 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -717,6 +717,8 @@ MPC8536DS_SDCARD powerpc mpc85xx mpc8536ds freesca + MPC8536DS_SPIFLASH powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SPIFLASH + MPC8540ADS powerpc mpc85xx mpc8540ads freescale + MPC8541CDS powerpc mpc85xx mpc8541cds freescale - MPC8541CDS ++QUANTA_LB9 powerpc mpc85xx quanta_lb9 quanta ++QUANTA_LB9-R0 powerpc mpc85xx quanta_lb9 quanta - QUANTA_LB9:ONIE_PLATFORM_REV=0 + MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY + MPC8544DS powerpc mpc85xx mpc8544ds freescale + MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS +diff --git a/common/cmd_ide.c b/common/cmd_ide.c +index 0105bdb..21b9697 100644 +--- a/common/cmd_ide.c ++++ b/common/cmd_ide.c +@@ -496,7 +496,7 @@ void ide_output_data(int dev, const ulong *sect_buf, int words) + __attribute__ ((weak, alias("__ide_output_data"))); + + /* We only need to swap data if we are running on a big endian cpu. */ +-#if defined(__LITTLE_ENDIAN) ++#if defined(__LITTLE_ENDIAN) || defined(CONFIG_IDE_SWAP_IO) + void __ide_input_swap_data(int dev, ulong *sect_buf, int words) + { + ide_input_data(dev, sect_buf, words); +diff --git a/config.mk b/config.mk +index b7cd481..12c3afd 100644 +--- a/config.mk ++++ b/config.mk +@@ -189,7 +189,7 @@ endif + # who are porting old code to latest mainline but not updating $(AR). + ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR) + RELFLAGS= $(PLATFORM_RELFLAGS) +-DBGFLAGS= -g # -DDEBUG ++DBGFLAGS= -g #-DDEBUG + OPTFLAGS= -Os #-fomit-frame-pointer + + OBJCFLAGS += --gap-fill=0xff +diff --git a/include/configs/QUANTA_LB9.h b/include/configs/QUANTA_LB9.h +new file mode 100644 +index 0000000..25cae8e +--- /dev/null ++++ b/include/configs/QUANTA_LB9.h +@@ -0,0 +1,434 @@ ++/* ++ * Copyright 2004, 2011 Freescale Semiconductor. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * mpc8541cds board configuration file ++ * ++ * Please refer to doc/README.mpc85xxcds for more info. ++ * ++ */ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#include "configs/common_config.h" ++ ++/* High Level Configuration Options */ ++#define CONFIG_BOOKE 1 /* BOOKE */ ++#define CONFIG_E500 1 /* BOOKE e500 family */ ++#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ ++#define CONFIG_CPM2 1 /* has CPM2 */ ++#define CONFIG_MPC8541 1 /* MPC8541 specific */ ++#define CONFIG_QUANTA_LB9 1 ++ ++#define CONFIG_PCI ++#define CONFIG_PCI1 ++#define CONFIG_TSEC_ENET /* tsec ethernet support */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ ++ ++#define CONFIG_SYS_CLK_FREQ 66000000 ++/*#define CONFIG_DDR_CLK_FREQ 66666666*/ ++ ++/* ++ * These can be toggled for performance analysis, otherwise use default. ++ */ ++#define CONFIG_L2_CACHE /* toggle L2 cache */ ++#define CONFIG_BTB /* toggle branch predition */ ++ ++#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ ++#define CONFIG_SYS_MEMTEST_END 0x00400000 ++ ++#define CONFIG_SYS_CCSRBAR 0xe0000000 ++#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR ++ ++/* DDR Setup */ ++#define CONFIG_FSL_DDR1 ++#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ ++#define CONFIG_DDR_SPD ++#undef CONFIG_FSL_DDR_INTERACTIVE ++ ++#define CONFIG_MEM_INIT_VALUE 0xDeadBeef ++ ++#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ ++#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE ++ ++#define CONFIG_NUM_DDR_CONTROLLERS 1 ++#define CONFIG_DIMM_SLOTS_PER_CTLR 1 ++#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) ++ ++/* I2C addresses of SPD EEPROMs */ ++#define SPD_EEPROM_ADDRESS 0x57 /* CTLR 0 DIMM 0 */ ++ ++/* ++ * Make sure required options are set ++ */ ++#ifndef CONFIG_SPD_EEPROM ++#error ("CONFIG_SPD_EEPROM is required by LB9") ++#endif ++ ++#undef CONFIG_CLOCKS_IN_MHZ ++ ++/* ++ * Local Bus Definitions ++ */ ++ ++#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* boot flash */ ++#define CONFIG_SYS_FLASH2_BASE 0xfc000000 /* 2nd flash */ ++#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE ++#define CONFIG_SYS_FLASH2_BASE_PHYS CONFIG_SYS_FLASH2_BASE ++ ++#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) ++#define CONFIG_FLASH2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH2_BASE_PHYS) | BR_PS_16 | BR_V) ++ ++#define CONFIG_FLASH_OR_PRELIM 0xfe007e65 /* 32M */ ++#define CONFIG_FLASH2_OR_PRELIM 0xfe007e65 /* 32M */ ++ ++#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ ++#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ ++#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH2_BR_PRELIM /* NOR Base Address */ ++#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH2_OR_PRELIM /* NOR Options */ ++ ++#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE} ++#define CONFIG_SYS_FLASH_QUIET_TEST ++#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ ++ ++#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ ++#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ ++ ++#define CFG_FLASH_SECT_SIZE 0x20000 /* 128k bytes per sector */ ++#define CFG_FLASH_SECT_OFFSET_MASK (CFG_FLASH_SECT_SIZE-1) ++#define CFG_FLASH_SECT_MASK (~CFG_FLASH_SECT_OFFSET_MASK) ++ ++#undef CONFIG_SYS_FLASH_CHECKSUM ++#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ ++#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ ++ ++#define CONFIG_SYS_TEXT_BASE 0xfff80000 ++ ++#ifndef CONFIG_SYS_MONITOR_BASE ++#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ ++#endif ++ ++#define CONFIG_FLASH_CFI_DRIVER ++#define CONFIG_SYS_FLASH_CFI ++#define CONFIG_SYS_FLASH_EMPTY_INFO ++ ++/* ++ * Compact FLASH on the Local Bus ++ * Two bank, 1M, using the IDE driver. ++ * ++ * BR5,BR2: ++ * Base address 5 = 0xF000_0000 = BR5[0:16] = 1111 0000 0000 0000 0 ++ * Base address 2 = 0xF001_0000 = BR2[0:16] = 1111 0000 0000 0001 0 ++ * Port Size = 32 bits = BRx[19:20] = 11 ++ * Use GPCM = BRx[24:26] = 000 ++ * Valid = BRx[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0000 0000 0000 0001 1000 0000 0001 = f0001801 BR5 ++ * 1111 0000 0000 0001 0001 1000 0000 0001 = f0011801 BR2 ++ * ++ * OR5, OR2: ++ * Addr Mask = 64K = ORx[0:16] = 1111 1111 1111 1111 0 ++ * Reserved ORx[17:18] = 11, confusion here? ++ * BCTLD = LBCTL not asserted = ORx[19] = 0 ++ * CSNT = ORx[20] = 1 ++ * ACS = half cycle delay = ORx[21:22] = 00 ++ * XACS = no extra setup = ORx[23] = 0 ++ * SCY = 10 = ORx[24:27] = 1010 ++ * SETA = cycle terminated internaly = ORx[28] = 0 ++ * TRLX = use relaxed timing = ORx[29] = 0 ++ * EHTR = use relaxed timing = ORx[30] = 0 ++ * EAD = use external address latch delay = OR[31] = 0 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 1111 1000 0000 0110 1000 1010 0000 = ffFF68A0 ORx ++ * 1111 1111 1000 0000 0110 1000 1010 0000 = ffFF68A0 ORx ++ */ ++ ++#define CONFIG_SYS_CFCARD0_BASE 0xf0000000 /* start of compact Flash */ ++#define CONFIG_SYS_CFCARD0_BASE_PHYS CONFIG_SYS_CFCARD0_BASE ++#define CONFIG_SYS_CFCARD1_BASE 0xf0010000 /* start of compact Flash */ ++#define CONFIG_SYS_CFCARD1_BASE_PHYS CONFIG_SYS_CFCARD1_BASE ++ ++#define CONFIG_SYS_BR5_PRELIM 0xf0001801 ++#define CONFIG_SYS_BR2_PRELIM 0xf0011801 ++ ++#define CONFIG_SYS_OR5_PRELIM 0xffff68A0 /* 64k */ ++#define CONFIG_SYS_OR2_PRELIM 0xffff68A0 /* 64k */ ++ ++ ++/* ++ * CPLD on the Local Bus ++ * One bank, 1M, using the IDE driver. ++ * ++ * BR4: ++ * Base address = 0xF200_0000 = BRx[0:16] = 1111 0010 0000 0000 0 ++ * Port Size = 32 bits = BRx[19:20] = 11 ++ * Use GPCM = BRx[24:26] = 000 ++ * Valid = BRx[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0010 0000 0010 0001 0000 0000 0001 = F2001801 BR4 ++ * ++ * OR4: ++ * Addr Mask = 64K = ORx[0:16] = 1111 1111 1111 1111 0 ++ * Reserved ORx[17:18] = 11, confusion here? ++ * BCTLD = LBCTL not asserted = ORx[19] = 1 ++ * CSNT = ORx[20] = 0 ++ * ACS = half cycle delay = ORx[21:22] = 11 ++ * XACS = no extra setup = ORx[23] = 0 ++ * SCY = 6 = ORx[24:27] = 0110 ++ * SETA = cycle terminated internaly = ORx[28] = 0 ++ * TRLX = use relaxed timing = ORx[29] = 1 ++ * EHTR = use relaxed timing = ORx[30] = 0 ++ * EAD = use external address latch delay = OR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 1111 1000 0000 0111 0110 0110 0101 = ffff7665 ORx ++ */ ++#define CPLD_SYS_BASE_ADDR 0xf2000000 ++#define CONFIG_SYS_BR4_PRELIM 0xf2001801 ++#define CONFIG_SYS_OR4_PRELIM 0xffff7665 ++ ++ ++ ++/*#define CONFIG_SYS_INIT_RAM_LOCK 1*/ ++#define CONFIG_SYS_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ ++#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ ++ ++#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) ++#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET ++ ++#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ ++#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ ++ ++/* Serial Port */ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_SYS_NS16550 ++#define CONFIG_SYS_NS16550_SERIAL ++#define CONFIG_SYS_NS16550_REG_SIZE 1 ++#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) ++ ++#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) ++#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) ++ ++/* Use the HUSH parser */ ++#define CONFIG_SYS_HUSH_PARSER ++#ifdef CONFIG_SYS_HUSH_PARSER ++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " ++#endif ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_LIBFDT 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++#define CONFIG_OF_STDOUT_VIA_ALIAS 1 ++ ++/* ++ * I2C ++ */ ++#define CONFIG_CMD_EEPROM /* EEPROM read/write support */ ++/* ++ * bit of hack to enable reading MAC from EEPROM w/o using Freescale's ++ * 'mac' command. Just having it defined enables the infra to call ++ * our mac_read_from_eeprom() to set $ethaddr. ++ * ++ */ ++#define CONFIG_SYS_I2C_MAC_OFFSET ++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 ++#define CONFIG_SYS_I2C_EEPROM_INFO_ADDR 0x0 ++#define CONFIG_SYS_I2C_EEPROM_INFO_LEN 0x0 ++ ++#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ ++#define CONFIG_HARD_I2C /* I2C with hardware support*/ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_I2C_CMD_TREE ++#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CONFIG_SYS_EEPROM_BUS_NUM 0 ++#define CONFIG_I2C_EEPROM_ADDR 0x53 ++#define CONFIG_SYS_I2C_SLAVE 0x7F ++#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ ++#define CONFIG_SYS_I2C_OFFSET 0x3000 ++ ++/* ++ * Quanta Board Info ++ */ ++ ++#define CONFIG_QUANTA_SOFT_VERSION 0xffffffff ++#define I2C_AT24C02_EEPROM_MB 0x53 ++#define EEPROM_24C02_SIZE 256 ++#define MODEL_NAME CONFIG_QUANTA_MODEL_NAME ++#define CONFIG_QUANTA_MODEL_NAME "LB9" ++ ++/* ++ * General PCI ++ * Memory space is mapped 1-1, but I/O space must start from 0. ++ */ ++#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 ++#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 ++#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 ++#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ ++#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 ++#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 ++#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 ++#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ ++ ++#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 ++#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 ++#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 ++#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ ++#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 ++#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 ++#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 ++#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ ++ ++#if defined(CONFIG_PCI) ++ ++#undef CONFIG_MPC85XX_PCI2 /* disabled */ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ ++#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ ++ ++#endif /* CONFIG_PCI */ ++ ++ ++#if defined(CONFIG_TSEC_ENET) ++ ++#ifndef CONFIG_NET_MULTI ++#define CONFIG_NET_MULTI 1 ++#endif ++ ++#define CONFIG_MII 1 /* MII PHY management */ ++#define CONFIG_TSEC1 1 ++#define CONFIG_TSEC1_NAME "eth0" ++#define TSEC1_PHY_ADDR 0 ++#define TSEC1_PHYIDX 0 ++#define TSEC1_FLAGS TSEC_GIGABIT ++ ++/* Options are: TSEC[0-1] */ ++#define CONFIG_ETHPRIME "eth0" ++ ++#endif /* CONFIG_TSEC_ENET */ ++ ++/* ++ * Environment ++ */ ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#define CONFIG_ENV_ADDR 0xfff60000 ++#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector for env */ ++#define CONFIG_ENV_SIZE 0x2000 ++#define CONFIG_ENV_OFFSET 0 ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++/* ++ * BOOTP options ++ */ ++#define CONFIG_BOOTP_BOOTFILESIZE ++#define CONFIG_BOOTP_BOOTPATH ++#define CONFIG_BOOTP_GATEWAY ++#define CONFIG_BOOTP_HOSTNAME ++ ++/* ++ * Command line configuration. ++ */ ++#include ++ ++#define CONFIG_CMD_PING ++#define CONFIG_CMD_I2C ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_ELF ++#define CONFIG_CMD_IRQ ++#define CONFIG_CMD_SETEXPR ++#define CONFIG_CMD_REGINFO ++ ++#if defined(CONFIG_PCI) ++ #define CONFIG_CMD_PCI ++#endif ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++#if 1 ++#define CONFIG_CMD_IDE ++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#define CONFIG_IDE_RESET 1 /* reset for ide supported */ ++#define CONFIG_IDE_PREINIT 1 /* call board specific ide init */ ++ ++#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ ++#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ ++ ++#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 ++#define CONFIG_SYS_ATA_IDE0_OFFSET 0 ++ ++#define CONFIG_SYS_ATA_DATA_OFFSET 2 /* Offset for data I/O */ ++#define CONFIG_SYS_ATA_REG_OFFSET 3 /* Offset for normal register accesses */ ++#define CONFIG_SYS_ATA_ALT_OFFSET 0x10000 /* Offset for alternate registers */ ++#define CONFIG_SYS_ATA_STRIDE 4 ++#define CONFIG_IDE_SWAP_IO ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ ++#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ ++/* enable platform specific init */ ++#define CONFIG_MISC_INIT_R 1 ++ ++#if defined(CONFIG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Environment Configuration ++ */ ++ ++/* The mac addresses for all ethernet interface */ ++#if defined(CONFIG_TSEC_ENET) ++#define CONFIG_HAS_ETH0 ++#endif ++ ++#define CONFIG_HOSTNAME quanta-lb9-unknown ++ ++/* default location for tftp and bootm */ ++#define CONFIG_LOADADDR 0x08000000 ++ ++/* ++ * Platform environment variables needed by the common env ++ * infrastructure. ++ * ++ */ ++#define CONFIG_PLATFORM_ENV \ ++ "consoledev=ttyS0\0" \ ++ "onie_start=0xffb60000\0" \ ++ "onie_sz.b=0x00400000\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_PLATFORM_ENV \ ++ CONFIG_ONIE_COMMON_UBOOT_ENV ++ ++#endif /* __CONFIG_H */ diff --git a/machine/quanta/quanta_lb9/u-boot/series b/machine/quanta/quanta_lb9/u-boot/series new file mode 100755 index 000000000..7ab22a5ca --- /dev/null +++ b/machine/quanta/quanta_lb9/u-boot/series @@ -0,0 +1,2 @@ +# This series applies on GIT commit ea0fcbbfb6db6f966f7f300b42e7d6419de9a8a8 +platform-quanta-lb9.patch