[AMDGPU] Constrain inline asm vgprs to low 256 (#157531)

Also adds codegen test for high VGPRs codegen.

Author: rampitec

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -17000,7 +17000,9 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
                                              : &AMDGPU::VGPR_32_Lo256RegClass;
         break;
       default:
-        RC = TRI->getVGPRClassForBitWidth(BitWidth);
+        RC = Subtarget->has1024AddressableVGPRs()
+                 ? TRI->getAlignedLo256VGPRClassForBitWidth(BitWidth)
+                 : TRI->getVGPRClassForBitWidth(BitWidth);
         if (!RC)
           return std::pair(0U, nullptr);
         break;