[RISCVISel] Compute leading zeros for RISCVISD::VCPOP_VL node

Author: vbe-sc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -19462,6 +19462,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known = Known.intersectWith(Known2);
     break;
   }
+  case RISCVISD::VCPOP_VL: {
+    KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(2), Depth + 1);
+    Known.Zero.setBitsFrom(Known2.countMaxActiveBits());
+    break;
+  }
   case RISCVISD::CZERO_EQZ:
   case RISCVISD::CZERO_NEZ:
     Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);

llvm/test/CodeGen/RISCV/rvv/vcpop-compute-known-bits.ll

@@ -7,7 +7,6 @@ define i32 @test(<8 x i1> %mask) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 255
 ; CHECK-NEXT:    ret
     %1 = bitcast <8 x i1> %mask to i8
     %2 = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 %1)

llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll

@@ -38,8 +38,7 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
 ; RV32-NEXT:    vcpop.m a7, v10
 ; RV32-NEXT:    vsetvli zero, a7, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v12, (a0)
-; RV32-NEXT:    slli a7, a7, 26
-; RV32-NEXT:    srli a7, a7, 24
+; RV32-NEXT:    slli a7, a7, 2
 ; RV32-NEXT:    or t0, t0, a6
 ; RV32-NEXT:    add a0, a0, a7
 ; RV32-NEXT:    mv a7, t1
@@ -101,8 +100,7 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
 ; RV64-NEXT:    vcpop.m a7, v10
 ; RV64-NEXT:    vsetvli zero, a7, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v12, (a0)
-; RV64-NEXT:    slli a7, a7, 58
-; RV64-NEXT:    srli a7, a7, 56
+; RV64-NEXT:    slli a7, a7, 2
 ; RV64-NEXT:    add a0, a0, a7
 ; RV64-NEXT:    bne a6, a5, .LBB0_4
 ; RV64-NEXT:  # %bb.5: # %middle.block