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[TTI] Support scalable offsets in getScalingFactorCost
1 parent 321f831 commit 58204d6

10 files changed

+30
-21
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -835,8 +835,8 @@ class TargetTransformInfo {
835835
/// TODO: Handle pre/postinc as well.
836836
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
837837
int64_t BaseOffset, bool HasBaseReg,
838-
int64_t Scale,
839-
unsigned AddrSpace = 0) const;
838+
int64_t Scale, unsigned AddrSpace = 0,
839+
int64_t ScalableOffset = 0) const;
840840

841841
/// Return true if the loop strength reduce pass should make
842842
/// Instruction* based TTI queries to isLegalAddressingMode(). This is
@@ -1894,7 +1894,8 @@ class TargetTransformInfo::Concept {
18941894
virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
18951895
int64_t BaseOffset,
18961896
bool HasBaseReg, int64_t Scale,
1897-
unsigned AddrSpace) = 0;
1897+
unsigned AddrSpace,
1898+
int64_t ScalableOffset) = 0;
18981899
virtual bool LSRWithInstrQueries() = 0;
18991900
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
19001901
virtual bool isProfitableToHoist(Instruction *I) = 0;
@@ -2406,10 +2407,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
24062407
}
24072408
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
24082409
int64_t BaseOffset, bool HasBaseReg,
2409-
int64_t Scale,
2410-
unsigned AddrSpace) override {
2410+
int64_t Scale, unsigned AddrSpace,
2411+
int64_t ScalableOffset) override {
24112412
return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2412-
AddrSpace);
2413+
AddrSpace, ScalableOffset);
24132414
}
24142415
bool LSRWithInstrQueries() override { return Impl.LSRWithInstrQueries(); }
24152416
bool isTruncateFree(Type *Ty1, Type *Ty2) override {

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -327,11 +327,11 @@ class TargetTransformInfoImplBase {
327327

328328
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
329329
int64_t BaseOffset, bool HasBaseReg,
330-
int64_t Scale,
331-
unsigned AddrSpace) const {
330+
int64_t Scale, unsigned AddrSpace,
331+
int64_t ScalableOffset) const {
332332
// Guess that all legal addressing mode are free.
333333
if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
334-
AddrSpace))
334+
AddrSpace, /*I=*/nullptr, ScalableOffset))
335335
return 0;
336336
return -1;
337337
}

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -406,12 +406,14 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
406406

407407
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
408408
int64_t BaseOffset, bool HasBaseReg,
409-
int64_t Scale, unsigned AddrSpace) {
409+
int64_t Scale, unsigned AddrSpace,
410+
int64_t ScalableOffset) {
410411
TargetLoweringBase::AddrMode AM;
411412
AM.BaseGV = BaseGV;
412413
AM.BaseOffs = BaseOffset;
413414
AM.HasBaseReg = HasBaseReg;
414415
AM.Scale = Scale;
416+
AM.ScalableOffset = ScalableOffset;
415417
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
416418
return 0;
417419
return -1;

‎llvm/lib/Analysis/TargetTransformInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -532,9 +532,9 @@ bool TargetTransformInfo::prefersVectorizedAddressing() const {
532532

533533
InstructionCost TargetTransformInfo::getScalingFactorCost(
534534
Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
535-
int64_t Scale, unsigned AddrSpace) const {
535+
int64_t Scale, unsigned AddrSpace, int64_t ScalableOffset) const {
536536
InstructionCost Cost = TTIImpl->getScalingFactorCost(
537-
Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
537+
Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace, ScalableOffset);
538538
assert(Cost >= 0 && "TTI should not produce negative costs!");
539539
return Cost;
540540
}

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4118,10 +4118,9 @@ bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
41184118
return NumInsns >= SVETailFoldInsnThreshold;
41194119
}
41204120

4121-
InstructionCost
4122-
AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
4123-
int64_t BaseOffset, bool HasBaseReg,
4124-
int64_t Scale, unsigned AddrSpace) const {
4121+
InstructionCost AArch64TTIImpl::getScalingFactorCost(
4122+
Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
4123+
int64_t Scale, unsigned AddrSpace, int64_t ScalableOffset) const {
41254124
// Scaling factors are not free at all.
41264125
// Operands | Rt Latency
41274126
// -------------------------------------------
@@ -4134,6 +4133,7 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
41344133
AM.BaseOffs = BaseOffset;
41354134
AM.HasBaseReg = HasBaseReg;
41364135
AM.Scale = Scale;
4136+
AM.ScalableOffset = ScalableOffset;
41374137
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
41384138
// Scale represents reg2 * scale, thus account for 1 if
41394139
// it is not equal to 0 or 1.

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,8 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
407407
/// If the AM is not supported, it returns a negative value.
408408
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
409409
int64_t BaseOffset, bool HasBaseReg,
410-
int64_t Scale, unsigned AddrSpace) const;
410+
int64_t Scale, unsigned AddrSpace,
411+
int64_t ScalableOffset) const;
411412
/// @}
412413

413414
bool enableSelectOptimize() { return ST->enableSelectOptimize(); }

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2572,12 +2572,14 @@ bool ARMTTIImpl::preferPredicatedReductionSelect(
25722572
InstructionCost ARMTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
25732573
int64_t BaseOffset,
25742574
bool HasBaseReg, int64_t Scale,
2575-
unsigned AddrSpace) const {
2575+
unsigned AddrSpace,
2576+
int64_t ScalableOffset) const {
25762577
TargetLoweringBase::AddrMode AM;
25772578
AM.BaseGV = BaseGV;
25782579
AM.BaseOffs = BaseOffset;
25792580
AM.HasBaseReg = HasBaseReg;
25802581
AM.Scale = Scale;
2582+
AM.ScalableOffset = ScalableOffset;
25812583
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) {
25822584
if (ST->hasFPAO())
25832585
return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,8 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
303303
/// If the AM is not supported, the return value must be negative.
304304
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
305305
int64_t BaseOffset, bool HasBaseReg,
306-
int64_t Scale, unsigned AddrSpace) const;
306+
int64_t Scale, unsigned AddrSpace,
307+
int64_t ScalableOffset) const;
307308

308309
bool maybeLoweredToCall(Instruction &I);
309310
bool isLoweredToCall(const Function *F);

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6670,7 +6670,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
66706670
InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
66716671
int64_t BaseOffset,
66726672
bool HasBaseReg, int64_t Scale,
6673-
unsigned AddrSpace) const {
6673+
unsigned AddrSpace,
6674+
int64_t ScalableOffset) const {
66746675
// Scaling factors are not free at all.
66756676
// An indexed folded instruction, i.e., inst (reg1, reg2, scale),
66766677
// will take 2 allocations in the out of order engine instead of 1

‎llvm/lib/Target/X86/X86TargetTransformInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,8 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
253253
/// If the AM is not supported, it returns a negative value.
254254
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
255255
int64_t BaseOffset, bool HasBaseReg,
256-
int64_t Scale, unsigned AddrSpace) const;
256+
int64_t Scale, unsigned AddrSpace,
257+
int64_t ScalableOffset) const;
257258

258259
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
259260
const TargetTransformInfo::LSRCost &C2);

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