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[AMDGPU] Remove AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough (#71407)
The special handling for blocks ending with a long branch has been unnecessary since D106445: "[amdgpu] Add 64-bit PC support when expanding unconditional branches."
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7 files changed

+23
-40
lines changed

7 files changed

+23
-40
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -148,20 +148,6 @@ void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
148148
}
149149
}
150150

151-
bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
152-
const MachineBasicBlock *MBB) const {
153-
if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
154-
return false;
155-
156-
if (MBB->empty())
157-
return true;
158-
159-
// If this is a block implementing a long branch, an expression relative to
160-
// the start of the block is needed. to the start of the block.
161-
// XXX - Is there a smarter way to check this?
162-
return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
163-
}
164-
165151
void AMDGPUAsmPrinter::emitFunctionBodyStart() {
166152
const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
167153
const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -128,9 +128,6 @@ class AMDGPUAsmPrinter final : public AsmPrinter {
128128

129129
void emitEndOfAsmFile(Module &M) override;
130130

131-
bool isBlockOnlyReachableByFallthrough(
132-
const MachineBasicBlock *MBB) const override;
133-
134131
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
135132
const char *ExtraCode, raw_ostream &O) override;
136133

‎llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ define amdgpu_kernel void @spill(ptr addrspace(1) %arg, i32 %cnd) #0 {
324324
; CHECK-NEXT: s_mov_b32 vcc_hi, 0
325325
; CHECK-NEXT: ;;#ASMEND
326326
; CHECK-NEXT: s_cbranch_scc0 .LBB0_1
327-
; CHECK-NEXT: .LBB0_3: ; %entry
327+
; CHECK-NEXT: ; %bb.3: ; %entry
328328
; CHECK-NEXT: s_not_b64 exec, exec
329329
; CHECK-NEXT: buffer_store_dword v0, off, s[96:99], 0
330330
; CHECK-NEXT: v_writelane_b32 v0, s0, 0
@@ -1290,7 +1290,7 @@ define void @spill_func(ptr addrspace(1) %arg) #0 {
12901290
; CHECK-NEXT: s_mov_b32 vcc_hi, 0
12911291
; CHECK-NEXT: ;;#ASMEND
12921292
; CHECK-NEXT: s_cbranch_scc0 .LBB1_1
1293-
; CHECK-NEXT: .LBB1_3: ; %entry
1293+
; CHECK-NEXT: ; %bb.3: ; %entry
12941294
; CHECK-NEXT: s_not_b64 exec, exec
12951295
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
12961296
; CHECK-NEXT: v_writelane_b32 v2, s0, 0

‎llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# block as the branch expansion.
55

66
# GCN-LABEL: long_branch_dbg_value:
7-
# GCN: .LBB0_5: ; %bb
7+
# GCN: ; %bb.5: ; %bb
88
# GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value]
99
# GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42
1010
# GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]

‎llvm/test/CodeGen/AMDGPU/branch-relaxation.ll‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs
6767
; GCN-NEXT: s_waitcnt lgkmcnt(0)
6868
; GCN-NEXT: s_cmp_eq_u32 s2, 0
6969
; GCN-NEXT: s_cbranch_scc0 .LBB1_1
70-
; GCN-NEXT: .LBB1_3: ; %bb0
70+
; GCN-NEXT: ; %bb.3: ; %bb0
7171
; GCN-NEXT: s_getpc_b64 s[4:5]
7272
; GCN-NEXT: .Lpost_getpc0:
7373
; GCN-NEXT: s_add_u32 s4, s4, (.LBB1_2-.Lpost_getpc0)&4294967295
@@ -115,7 +115,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
115115
; GCN-NEXT: v_cmp_eq_f32_e64 s[4:5], s2, 0
116116
; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
117117
; GCN-NEXT: s_cbranch_vccz .LBB2_1
118-
; GCN-NEXT: .LBB2_3: ; %bb0
118+
; GCN-NEXT: ; %bb.3: ; %bb0
119119
; GCN-NEXT: s_getpc_b64 s[4:5]
120120
; GCN-NEXT: .Lpost_getpc1:
121121
; GCN-NEXT: s_add_u32 s4, s4, (.LBB2_2-.Lpost_getpc1)&4294967295
@@ -172,7 +172,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
172172
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
173173
; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc
174174
; GCN-NEXT: s_cbranch_execnz .LBB3_1
175-
; GCN-NEXT: .LBB3_3: ; %bb
175+
; GCN-NEXT: ; %bb.3: ; %bb
176176
; GCN-NEXT: s_getpc_b64 s[4:5]
177177
; GCN-NEXT: .Lpost_getpc2:
178178
; GCN-NEXT: s_add_u32 s4, s4, (.LBB3_2-.Lpost_getpc2)&4294967295
@@ -228,7 +228,7 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
228228
; GCN-NEXT: v_nop_e64
229229
; GCN-NEXT: ;;#ASMEND
230230
; GCN-NEXT: s_cbranch_scc0 .LBB4_2
231-
; GCN-NEXT: .LBB4_3: ; %bb2
231+
; GCN-NEXT: ; %bb.3: ; %bb2
232232
; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1
233233
; GCN-NEXT: s_getpc_b64 s[2:3]
234234
; GCN-NEXT: .Lpost_getpc3:
@@ -266,7 +266,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
266266
; GCN-NEXT: s_cmp_eq_u32 s2, 0
267267
; GCN-NEXT: s_mov_b64 s[2:3], -1
268268
; GCN-NEXT: s_cbranch_scc0 .LBB5_1
269-
; GCN-NEXT: .LBB5_7: ; %bb0
269+
; GCN-NEXT: ; %bb.7: ; %bb0
270270
; GCN-NEXT: s_getpc_b64 s[2:3]
271271
; GCN-NEXT: .Lpost_getpc5:
272272
; GCN-NEXT: s_add_u32 s2, s2, (.LBB5_4-.Lpost_getpc5)&4294967295
@@ -299,7 +299,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
299299
; GCN-NEXT: v_nop_e64
300300
; GCN-NEXT: ;;#ASMEND
301301
; GCN-NEXT: s_cbranch_execnz .LBB5_5
302-
; GCN-NEXT: .LBB5_9: ; %bb3
302+
; GCN-NEXT: ; %bb.9: ; %bb3
303303
; GCN-NEXT: s_getpc_b64 s[2:3]
304304
; GCN-NEXT: .Lpost_getpc6:
305305
; GCN-NEXT: s_add_u32 s2, s2, (.LBB5_2-.Lpost_getpc6)&4294967295
@@ -347,7 +347,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad
347347
; GCN-NEXT: ;;#ASMEND
348348
; GCN-NEXT: s_mov_b64 vcc, vcc
349349
; GCN-NEXT: s_cbranch_vccz .LBB6_2
350-
; GCN-NEXT: .LBB6_3: ; %loop
350+
; GCN-NEXT: ; %bb.3: ; %loop
351351
; GCN-NEXT: ; in Loop: Header=BB6_1 Depth=1
352352
; GCN-NEXT: s_getpc_b64 s[0:1]
353353
; GCN-NEXT: .Lpost_getpc7:
@@ -389,7 +389,7 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
389389
; GCN-NEXT: .LBB7_2: ; %Flow
390390
; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1]
391391
; GCN-NEXT: s_cbranch_vccz .LBB7_3
392-
; GCN-NEXT: .LBB7_5: ; %Flow
392+
; GCN-NEXT: ; %bb.5: ; %Flow
393393
; GCN-NEXT: s_getpc_b64 s[0:1]
394394
; GCN-NEXT: .Lpost_getpc8:
395395
; GCN-NEXT: s_add_u32 s0, s0, (.LBB7_4-.Lpost_getpc8)&4294967295
@@ -446,7 +446,7 @@ define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %
446446
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
447447
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
448448
; GCN-NEXT: s_cbranch_execnz .LBB8_1
449-
; GCN-NEXT: .LBB8_4: ; %entry
449+
; GCN-NEXT: ; %bb.4: ; %entry
450450
; GCN-NEXT: s_getpc_b64 s[0:1]
451451
; GCN-NEXT: .Lpost_getpc9:
452452
; GCN-NEXT: s_add_u32 s0, s0, (.LBB8_3-.Lpost_getpc9)&4294967295
@@ -512,7 +512,7 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
512512
; GCN-NEXT: .LBB9_2: ; %Flow1
513513
; GCN-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
514514
; GCN-NEXT: s_cbranch_execnz .LBB9_3
515-
; GCN-NEXT: .LBB9_6: ; %Flow1
515+
; GCN-NEXT: ; %bb.6: ; %Flow1
516516
; GCN-NEXT: s_getpc_b64 s[0:1]
517517
; GCN-NEXT: .Lpost_getpc10:
518518
; GCN-NEXT: s_add_u32 s0, s0, (.LBB9_5-.Lpost_getpc10)&4294967295
@@ -534,7 +534,7 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
534534
; GCN-NEXT: ;;#ASMEND
535535
; GCN-NEXT: s_mov_b64 vcc, vcc
536536
; GCN-NEXT: s_cbranch_vccnz .LBB9_5
537-
; GCN-NEXT: .LBB9_8: ; %loop
537+
; GCN-NEXT: ; %bb.8: ; %loop
538538
; GCN-NEXT: ; in Loop: Header=BB9_4 Depth=1
539539
; GCN-NEXT: s_getpc_b64 s[0:1]
540540
; GCN-NEXT: .Lpost_getpc11:
@@ -580,7 +580,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
580580
; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0
581581
; GCN-NEXT: s_cmp_lt_i32 s7, 6
582582
; GCN-NEXT: s_cbranch_scc1 .LBB10_1
583-
; GCN-NEXT: .LBB10_8: ; %bb
583+
; GCN-NEXT: ; %bb.8: ; %bb
584584
; GCN-NEXT: s_getpc_b64 s[8:9]
585585
; GCN-NEXT: .Lpost_getpc12:
586586
; GCN-NEXT: s_add_u32 s8, s8, (.LBB10_2-.Lpost_getpc12)&4294967295
@@ -606,7 +606,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
606606
; GCN-NEXT: .LBB10_4: ; %Flow5
607607
; GCN-NEXT: s_andn2_b64 vcc, exec, s[8:9]
608608
; GCN-NEXT: s_cbranch_vccz .LBB10_5
609-
; GCN-NEXT: .LBB10_10: ; %Flow5
609+
; GCN-NEXT: ; %bb.10: ; %Flow5
610610
; GCN-NEXT: s_getpc_b64 s[2:3]
611611
; GCN-NEXT: .Lpost_getpc13:
612612
; GCN-NEXT: s_add_u32 s2, s2, (.LBB10_6-.Lpost_getpc13)&4294967295

‎llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ declare void @llvm.amdgcn.s.sleep(i32) #0
1111
; GCN-LABEL: {{^}}branch_offset_test:
1212
; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0
1313
; GCN-NEXT: s_cbranch_scc0 [[BB2:.LBB[0-9]+_[0-9]+]]
14-
; GCN-NEXT: .LBB{{[0-9]+}}_{{[0-9]+}}: ; %bb
14+
; GCN-NEXT: ; %bb.3: ; %bb
1515
; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
1616
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
1717
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295

‎llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs
5959
; GCN-NEXT: s_waitcnt lgkmcnt(0)
6060
; GCN-NEXT: s_cmp_eq_u32 s2, 0
6161
; GCN-NEXT: s_cbranch_scc0 .LBB1_1
62-
; GCN-NEXT: .LBB1_3: ; %bb0
62+
; GCN-NEXT: ; %bb.3: ; %bb0
6363
; GCN-NEXT: s_getpc_b64 s[8:9]
6464
; GCN-NEXT: .Lpost_getpc0:
6565
; GCN-NEXT: s_add_u32 s8, s8, (.LBB1_2-.Lpost_getpc0)&4294967295
@@ -107,7 +107,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
107107
; GCN-NEXT: v_cmp_eq_f32_e64 s[4:5], s2, 0
108108
; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
109109
; GCN-NEXT: s_cbranch_vccz .LBB2_1
110-
; GCN-NEXT: .LBB2_3: ; %bb0
110+
; GCN-NEXT: ; %bb.3: ; %bb0
111111
; GCN-NEXT: s_getpc_b64 s[8:9]
112112
; GCN-NEXT: .Lpost_getpc1:
113113
; GCN-NEXT: s_add_u32 s8, s8, (.LBB2_2-.Lpost_getpc1)&4294967295
@@ -164,7 +164,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
164164
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
165165
; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc
166166
; GCN-NEXT: s_cbranch_execnz .LBB3_1
167-
; GCN-NEXT: .LBB3_3: ; %bb
167+
; GCN-NEXT: ; %bb.3: ; %bb
168168
; GCN-NEXT: s_getpc_b64 s[4:5]
169169
; GCN-NEXT: .Lpost_getpc2:
170170
; GCN-NEXT: s_add_u32 s4, s4, (.LBB3_2-.Lpost_getpc2)&4294967295
@@ -220,7 +220,7 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
220220
; GCN-NEXT: v_nop_e64
221221
; GCN-NEXT: ;;#ASMEND
222222
; GCN-NEXT: s_cbranch_scc0 .LBB4_2
223-
; GCN-NEXT: .LBB4_3: ; %bb2
223+
; GCN-NEXT: ; %bb.3: ; %bb2
224224
; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1
225225
; GCN-NEXT: s_getpc_b64 s[2:3]
226226
; GCN-NEXT: .Lpost_getpc3:
@@ -259,7 +259,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
259259
; GCN-NEXT: s_cmp_eq_u32 s2, 0
260260
; GCN-NEXT: s_mov_b64 s[2:3], -1
261261
; GCN-NEXT: s_cbranch_scc0 .LBB5_1
262-
; GCN-NEXT: .LBB5_7: ; %bb0
262+
; GCN-NEXT: ; %bb.7: ; %bb0
263263
; GCN-NEXT: s_getpc_b64 s[4:5]
264264
; GCN-NEXT: .Lpost_getpc5:
265265
; GCN-NEXT: s_add_u32 s4, s4, (.LBB5_4-.Lpost_getpc5)&4294967295
@@ -293,7 +293,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
293293
; GCN-NEXT: ;;#ASMEND
294294
; GCN-NEXT: s_mov_b64 vcc, exec
295295
; GCN-NEXT: s_cbranch_execnz .LBB5_5
296-
; GCN-NEXT: .LBB5_9: ; %bb3
296+
; GCN-NEXT: ; %bb.9: ; %bb3
297297
; GCN-NEXT: s_getpc_b64 s[4:5]
298298
; GCN-NEXT: .Lpost_getpc6:
299299
; GCN-NEXT: s_add_u32 s4, s4, (.LBB5_2-.Lpost_getpc6)&4294967295

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