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[TTI] Support scalable offsets in getScalingFactorCost (#88113)
Part of the work to support vscale-relative immediates in LSR.
1 parent 64d4ade commit 2e8d815

11 files changed

+28
-20
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -834,7 +834,7 @@ class TargetTransformInfo {
834834
/// If the AM is not supported, it returns a negative value.
835835
/// TODO: Handle pre/postinc as well.
836836
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
837-
int64_t BaseOffset, bool HasBaseReg,
837+
StackOffset BaseOffset, bool HasBaseReg,
838838
int64_t Scale,
839839
unsigned AddrSpace = 0) const;
840840

@@ -1891,7 +1891,7 @@ class TargetTransformInfo::Concept {
18911891
virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
18921892
virtual bool prefersVectorizedAddressing() = 0;
18931893
virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
1894-
int64_t BaseOffset,
1894+
StackOffset BaseOffset,
18951895
bool HasBaseReg, int64_t Scale,
18961896
unsigned AddrSpace) = 0;
18971897
virtual bool LSRWithInstrQueries() = 0;
@@ -2403,7 +2403,7 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
24032403
return Impl.prefersVectorizedAddressing();
24042404
}
24052405
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2406-
int64_t BaseOffset, bool HasBaseReg,
2406+
StackOffset BaseOffset, bool HasBaseReg,
24072407
int64_t Scale,
24082408
unsigned AddrSpace) override {
24092409
return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ class Function;
3232
/// Base class for use as a mix-in that aids implementing
3333
/// a TargetTransformInfo-compatible class.
3434
class TargetTransformInfoImplBase {
35+
3536
protected:
3637
typedef TargetTransformInfo TTI;
3738

@@ -326,12 +327,13 @@ class TargetTransformInfoImplBase {
326327
bool prefersVectorizedAddressing() const { return true; }
327328

328329
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
329-
int64_t BaseOffset, bool HasBaseReg,
330+
StackOffset BaseOffset, bool HasBaseReg,
330331
int64_t Scale,
331332
unsigned AddrSpace) const {
332333
// Guess that all legal addressing mode are free.
333-
if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
334-
AddrSpace))
334+
if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg,
335+
Scale, AddrSpace, /*I=*/nullptr,
336+
BaseOffset.getScalable()))
335337
return 0;
336338
return -1;
337339
}

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -404,13 +404,14 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
404404
}
405405

406406
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
407-
int64_t BaseOffset, bool HasBaseReg,
407+
StackOffset BaseOffset, bool HasBaseReg,
408408
int64_t Scale, unsigned AddrSpace) {
409409
TargetLoweringBase::AddrMode AM;
410410
AM.BaseGV = BaseGV;
411-
AM.BaseOffs = BaseOffset;
411+
AM.BaseOffs = BaseOffset.getFixed();
412412
AM.HasBaseReg = HasBaseReg;
413413
AM.Scale = Scale;
414+
AM.ScalableOffset = BaseOffset.getScalable();
414415
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
415416
return 0;
416417
return -1;

‎llvm/lib/Analysis/TargetTransformInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -531,7 +531,7 @@ bool TargetTransformInfo::prefersVectorizedAddressing() const {
531531
}
532532

533533
InstructionCost TargetTransformInfo::getScalingFactorCost(
534-
Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
534+
Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
535535
int64_t Scale, unsigned AddrSpace) const {
536536
InstructionCost Cost = TTIImpl->getScalingFactorCost(
537537
Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4183,7 +4183,7 @@ bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
41834183

41844184
InstructionCost
41854185
AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
4186-
int64_t BaseOffset, bool HasBaseReg,
4186+
StackOffset BaseOffset, bool HasBaseReg,
41874187
int64_t Scale, unsigned AddrSpace) const {
41884188
// Scaling factors are not free at all.
41894189
// Operands | Rt Latency
@@ -4194,9 +4194,10 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
41944194
// Rt, [Xn, Wm, <extend> #imm] |
41954195
TargetLoweringBase::AddrMode AM;
41964196
AM.BaseGV = BaseGV;
4197-
AM.BaseOffs = BaseOffset;
4197+
AM.BaseOffs = BaseOffset.getFixed();
41984198
AM.HasBaseReg = HasBaseReg;
41994199
AM.Scale = Scale;
4200+
AM.ScalableOffset = BaseOffset.getScalable();
42004201
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
42014202
// Scale represents reg2 * scale, thus account for 1 if
42024203
// it is not equal to 0 or 1.

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,7 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
407407
/// If the AM is supported, the return value must be >= 0.
408408
/// If the AM is not supported, it returns a negative value.
409409
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
410-
int64_t BaseOffset, bool HasBaseReg,
410+
StackOffset BaseOffset, bool HasBaseReg,
411411
int64_t Scale, unsigned AddrSpace) const;
412412
/// @}
413413

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2571,14 +2571,15 @@ bool ARMTTIImpl::preferPredicatedReductionSelect(
25712571
}
25722572

25732573
InstructionCost ARMTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2574-
int64_t BaseOffset,
2574+
StackOffset BaseOffset,
25752575
bool HasBaseReg, int64_t Scale,
25762576
unsigned AddrSpace) const {
25772577
TargetLoweringBase::AddrMode AM;
25782578
AM.BaseGV = BaseGV;
2579-
AM.BaseOffs = BaseOffset;
2579+
AM.BaseOffs = BaseOffset.getFixed();
25802580
AM.HasBaseReg = HasBaseReg;
25812581
AM.Scale = Scale;
2582+
AM.ScalableOffset = BaseOffset.getScalable();
25822583
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) {
25832584
if (ST->hasFPAO())
25842585
return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,7 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
303303
/// If the AM is supported, the return value must be >= 0.
304304
/// If the AM is not supported, the return value must be negative.
305305
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
306-
int64_t BaseOffset, bool HasBaseReg,
306+
StackOffset BaseOffset, bool HasBaseReg,
307307
int64_t Scale, unsigned AddrSpace) const;
308308

309309
bool maybeLoweredToCall(Instruction &I);

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6741,7 +6741,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
67416741
}
67426742

67436743
InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
6744-
int64_t BaseOffset,
6744+
StackOffset BaseOffset,
67456745
bool HasBaseReg, int64_t Scale,
67466746
unsigned AddrSpace) const {
67476747
// Scaling factors are not free at all.
@@ -6764,9 +6764,10 @@ InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
67646764
// vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
67656765
TargetLoweringBase::AddrMode AM;
67666766
AM.BaseGV = BaseGV;
6767-
AM.BaseOffs = BaseOffset;
6767+
AM.BaseOffs = BaseOffset.getFixed();
67686768
AM.HasBaseReg = HasBaseReg;
67696769
AM.Scale = Scale;
6770+
AM.ScalableOffset = BaseOffset.getScalable();
67706771
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
67716772
// Scale represents reg2 * scale, thus account for 1
67726773
// as soon as we use a second register.

‎llvm/lib/Target/X86/X86TargetTransformInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,7 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
253253
/// If the AM is supported, the return value must be >= 0.
254254
/// If the AM is not supported, it returns a negative value.
255255
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
256-
int64_t BaseOffset, bool HasBaseReg,
256+
StackOffset BaseOffset, bool HasBaseReg,
257257
int64_t Scale, unsigned AddrSpace) const;
258258

259259
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,

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