[CIR][CIRGen][Builtin][Neon] Lower vrsrad_n u64 and s64 (#1379)

Lower vrsrad_n u64 and s64

Author: AmrDeveloper

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -3840,7 +3840,21 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
   }
   case NEON::BI__builtin_neon_vrsrad_n_u64:
   case NEON::BI__builtin_neon_vrsrad_n_s64: {
-    llvm_unreachable("NEON::BI__builtin_neon_vrsrad_n_s64 NYI");
+    cir::IntType IntType = BuiltinID == NEON::BI__builtin_neon_vrsrad_n_u64
+                               ? builder.getUInt64Ty()
+                               : builder.getSInt64Ty();
+    Ops[1] = builder.createBitcast(Ops[1], IntType);
+    Ops.push_back(builder.createNeg(emitScalarExpr(E->getArg(2))));
+
+    const StringRef Intrinsic = BuiltinID == NEON::BI__builtin_neon_vrsrad_n_u64
+                                    ? "aarch64.neon.urshl"
+                                    : "aarch64.neon.srshl";
+
+    llvm::SmallVector<mlir::Value, 2> args = {
+        Ops[1], builder.createIntCast(Ops[2], IntType)};
+    Ops[1] = emitNeonCall(builder, {IntType, IntType}, args, Intrinsic, IntType,
+                          getLoc(E->getExprLoc()));
+    return builder.createAdd(Ops[0], builder.createBitcast(Ops[1], IntType));
   }
   case NEON::BI__builtin_neon_vshld_n_s64:
   case NEON::BI__builtin_neon_vshld_n_u64: {

clang/test/CIR/CodeGen/AArch64/neon.c

@@ -15327,13 +15327,21 @@ uint64x1_t test_vsra_n_u64(uint64x1_t a, uint64x1_t b) {
   // LLVM:   ret <1 x i64> [[TMP4]]
 }
 
-// NYI-LABEL: @test_vrsrad_n_s64(
-// NYI:   [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 %b, i64 -63)
-// NYI:   [[TMP1:%.*]] = add i64 %a, [[TMP0]]
-// NYI:   ret i64 [[TMP1]]
-// int64_t test_vrsrad_n_s64(int64_t a, int64_t b) {
-//   return (int64_t)vrsrad_n_s64(a, b, 63);
-// }
+int64_t test_vrsrad_n_s64(int64_t a, int64_t b) {
+  return (int64_t)vrsrad_n_s64(a, b, 63);
+
+  // CIR-LABEL: vrsrad_n_s64
+  // CIR: [[TMP0:%.*]] = cir.const #cir.int<63> : !s32i
+  // CIR: [[TMP1:%.*]] = cir.unary(minus, [[TMP0]]) : !s32i, !s32i
+  // CIR: [[TMP2:%.*]] = cir.cast(integral, [[TMP1]] : !s32i), !s64i
+  // CIR: [[TMP3:%.*]] = cir.llvm.intrinsic "aarch64.neon.srshl" {{.*}}, [[TMP2]] : (!s64i, !s64i) -> !s64i
+  // CIR: [[TMP4:%.*]] = cir.binop(add, {{.*}}, [[TMP3]]) : !s64i
+
+  // LLVM-LABEL: @test_vrsrad_n_s64(
+  // LLVM: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 %1, i64 -63)
+  // LLVM: [[TMP1:%.*]] = add i64 %0, [[TMP0]]
+  // LLVM: ret i64 [[TMP1]]
+}
 
 int64x1_t test_vrsra_n_s64(int64x1_t a, int64x1_t b) {
   return vrsra_n_s64(a, b, 1);
@@ -15355,13 +15363,21 @@ int64x1_t test_vrsra_n_s64(int64x1_t a, int64x1_t b) {
   // LLVM:   ret <1 x i64> [[TMP3]]
 }
 
-// NYI-LABEL: @test_vrsrad_n_u64(
-// NYI:   [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 %b, i64 -63)
-// NYI:   [[TMP1:%.*]] = add i64 %a, [[TMP0]]
-// NYI:   ret i64 [[TMP1]]
-// uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) {
-//   return (uint64_t)vrsrad_n_u64(a, b, 63);
-// }
+uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) {
+  return (uint64_t)vrsrad_n_u64(a, b, 63);
+
+  // CIR-LABEL:vrsrad_n_u64
+  // CIR: [[TMP0:%.*]] = cir.const #cir.int<63> : !s32i
+  // CIR: [[TMP1:%.*]] = cir.unary(minus, [[TMP0]]) : !s32i, !s32i
+  // CIR: [[TMP2:%.*]] = cir.cast(integral, [[TMP1]] : !s32i), !u64i
+  // CIR: [[TMP3:%.*]] = cir.llvm.intrinsic "aarch64.neon.urshl" {{.*}}, [[TMP2]] : (!u64i, !u64i) -> !u64i
+  // CIR: [[TMP4:%.*]] = cir.binop(add, {{.*}}, [[TMP3]]) : !u64i
+
+  // LLVM-LABEL: @test_vrsrad_n_u64(
+  // LLVM: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 %1, i64 -63)
+  // LLVM: [[TMP1:%.*]] = add i64 %0, [[TMP0]]
+  // LLVM: ret i64 [[TMP1]]
+}
 
 uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) {
   return vrsra_n_u64(a, b, 1);