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[LLVM][TableGen] Change InstrInfoEmitter to use const RecordKeeper (llvm#109189)
Change InstrInfoEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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7 files changed

+34
-32
lines changed

7 files changed

+34
-32
lines changed

‎llvm/utils/TableGen/Common/CodeGenInstruction.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -485,8 +485,8 @@ CodeGenInstruction::CodeGenInstruction(const Record *R)
485485
isCodeGenOnly = R->getValueAsBit("isCodeGenOnly");
486486
isPseudo = R->getValueAsBit("isPseudo");
487487
isMeta = R->getValueAsBit("isMeta");
488-
ImplicitDefs = R->getValueAsListOfDefs("Defs");
489-
ImplicitUses = R->getValueAsListOfDefs("Uses");
488+
ImplicitDefs = R->getValueAsListOfConstDefs("Defs");
489+
ImplicitUses = R->getValueAsListOfConstDefs("Uses");
490490

491491
// This flag is only inferred from the pattern.
492492
hasChain = false;
@@ -523,7 +523,7 @@ MVT::SimpleValueType CodeGenInstruction::HasOneImplicitDefWithKnownVT(
523523
return MVT::Other;
524524

525525
// Check to see if the first implicit def has a resolvable type.
526-
Record *FirstImplicitDef = ImplicitDefs[0];
526+
const Record *FirstImplicitDef = ImplicitDefs[0];
527527
assert(FirstImplicitDef->isSubClassOf("Register"));
528528
const std::vector<ValueTypeByHwMode> &RegVTs =
529529
TargetInfo.getRegisterVTs(FirstImplicitDef);

‎llvm/utils/TableGen/Common/CodeGenInstruction.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -235,7 +235,7 @@ class CodeGenInstruction {
235235

236236
/// ImplicitDefs/ImplicitUses - These are lists of registers that are
237237
/// implicitly defined and used by the instruction.
238-
std::vector<Record *> ImplicitDefs, ImplicitUses;
238+
std::vector<const Record *> ImplicitDefs, ImplicitUses;
239239

240240
// Various boolean values we track for the instruction.
241241
bool isPreISelOpcode : 1;

‎llvm/utils/TableGen/Common/CodeGenTarget.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,8 @@ CodeGenTarget::getRegisterClass(const Record *R) const {
234234
return *getRegBank().getRegClass(R);
235235
}
236236

237-
std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) const {
237+
std::vector<ValueTypeByHwMode>
238+
CodeGenTarget::getRegisterVTs(const Record *R) const {
238239
const CodeGenRegister *Reg = getRegBank().getReg(R);
239240
std::vector<ValueTypeByHwMode> Result;
240241
for (const auto &RC : getRegBank().getRegClasses()) {

‎llvm/utils/TableGen/Common/CodeGenTarget.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ class CodeGenTarget {
144144

145145
/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
146146
/// specified physical register.
147-
std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
147+
std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;
148148

149149
ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
150150
if (LegalValueTypes.empty())

‎llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2337,7 +2337,7 @@ class BuildMIAction : public MatchAction {
23372337
const CodeGenInstruction *I;
23382338
InstructionMatcher *Matched;
23392339
std::vector<std::unique_ptr<OperandRenderer>> OperandRenderers;
2340-
SmallPtrSet<Record *, 4> DeadImplicitDefs;
2340+
SmallPtrSet<const Record *, 4> DeadImplicitDefs;
23412341

23422342
std::vector<const InstructionMatcher *> CopiedFlags;
23432343
std::vector<StringRef> SetFlags;
@@ -2365,7 +2365,7 @@ class BuildMIAction : public MatchAction {
23652365

23662366
void chooseInsnToMutate(RuleMatcher &Rule);
23672367

2368-
void setDeadImplicitDef(Record *R) { DeadImplicitDefs.insert(R); }
2368+
void setDeadImplicitDef(const Record *R) { DeadImplicitDefs.insert(R); }
23692369

23702370
template <class Kind, class... Args> Kind &addRenderer(Args &&...args) {
23712371
OperandRenderers.emplace_back(

‎llvm/utils/TableGen/GlobalISelEmitter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2368,7 +2368,7 @@ void GlobalISelEmitter::emitRunCustomAction(raw_ostream &OS) {
23682368
}
23692369

23702370
void GlobalISelEmitter::postProcessRule(RuleMatcher &M) {
2371-
SmallPtrSet<Record *, 16> UsedRegs;
2371+
SmallPtrSet<const Record *, 16> UsedRegs;
23722372

23732373
// TODO: deal with subregs?
23742374
for (auto &A : M.actions()) {

‎llvm/utils/TableGen/InstrInfoEmitter.cpp‎

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,12 @@ static cl::opt<bool> ExpandMIOperandInfo(
4848
namespace {
4949

5050
class InstrInfoEmitter {
51-
RecordKeeper &Records;
52-
CodeGenDAGPatterns CDP;
51+
const RecordKeeper &Records;
52+
const CodeGenDAGPatterns CDP;
5353
const CodeGenSchedModels &SchedModels;
5454

5555
public:
56-
InstrInfoEmitter(RecordKeeper &R)
56+
InstrInfoEmitter(const RecordKeeper &R)
5757
: Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
5858

5959
// run - Output the instruction set description.
@@ -88,8 +88,8 @@ class InstrInfoEmitter {
8888
/// Write verifyInstructionPredicates methods.
8989
void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
9090
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
91-
Record *InstrInfo,
92-
std::map<std::vector<Record *>, unsigned> &EL,
91+
const Record *InstrInfo,
92+
std::map<std::vector<const Record *>, unsigned> &EL,
9393
const OperandInfoMapTy &OperandInfo, raw_ostream &OS);
9494
void emitOperandTypeMappings(
9595
raw_ostream &OS, const CodeGenTarget &Target,
@@ -136,7 +136,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
136136
// registers in their multi-operand operands. It may also be an anonymous
137137
// operand, which has a single operand, but no declared class for the
138138
// operand.
139-
DagInit *MIOI = Op.MIOperandInfo;
139+
const DagInit *MIOI = Op.MIOperandInfo;
140140

141141
if (!MIOI || MIOI->getNumArgs() == 0) {
142142
// Single, anonymous, operand.
@@ -356,10 +356,11 @@ void InstrInfoEmitter::emitOperandTypeMappings(
356356
ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
357357

358358
StringRef Namespace = Target.getInstNamespace();
359-
std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
360-
std::vector<Record *> RegisterOperands =
359+
ArrayRef<const Record *> Operands =
360+
Records.getAllDerivedDefinitions("Operand");
361+
ArrayRef<const Record *> RegisterOperands =
361362
Records.getAllDerivedDefinitions("RegisterOperand");
362-
std::vector<Record *> RegisterClasses =
363+
ArrayRef<const Record *> RegisterClasses =
363364
Records.getAllDerivedDefinitions("RegisterClass");
364365

365366
OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
@@ -370,9 +371,9 @@ void InstrInfoEmitter::emitOperandTypeMappings(
370371
OS << "enum OperandType {\n";
371372

372373
unsigned EnumVal = 0;
373-
for (const std::vector<Record *> *RecordsToAdd :
374-
{&Operands, &RegisterOperands, &RegisterClasses}) {
375-
for (const Record *Op : *RecordsToAdd) {
374+
for (ArrayRef<const Record *> RecordsToAdd :
375+
{Operands, RegisterOperands, RegisterClasses}) {
376+
for (const Record *Op : RecordsToAdd) {
376377
if (!Op->isAnonymous())
377378
OS << " " << Op->getName() << " = " << EnumVal << ",\n";
378379
++EnumVal;
@@ -764,8 +765,8 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
764765
}
765766
}
766767

767-
llvm::sort(FeatureBitsets, [&](const std::vector<const Record *> &A,
768-
const std::vector<const Record *> &B) {
768+
llvm::sort(FeatureBitsets, [&](ArrayRef<const Record *> A,
769+
ArrayRef<const Record *> B) {
769770
if (A.size() < B.size())
770771
return true;
771772
if (A.size() > B.size())
@@ -928,9 +929,9 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
928929
emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
929930
emitEnums(OS);
930931

931-
CodeGenTarget &Target = CDP.getTargetInfo();
932+
const CodeGenTarget &Target = CDP.getTargetInfo();
932933
const std::string &TargetName = std::string(Target.getName());
933-
Record *InstrInfo = Target.getInstructionSet();
934+
const Record *InstrInfo = Target.getInstructionSet();
934935

935936
// Collect all of the operand info records.
936937
Records.startTimer("Collect operand info");
@@ -941,11 +942,11 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
941942

942943
// Collect all of the instruction's implicit uses and defs.
943944
Records.startTimer("Collect uses/defs");
944-
std::map<std::vector<Record *>, unsigned> EmittedLists;
945-
std::vector<std::vector<Record *>> ImplicitLists;
945+
std::map<std::vector<const Record *>, unsigned> EmittedLists;
946+
std::vector<std::vector<const Record *>> ImplicitLists;
946947
unsigned ImplicitListSize = 0;
947948
for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
948-
std::vector<Record *> ImplicitOps = II->ImplicitUses;
949+
std::vector<const Record *> ImplicitOps = II->ImplicitUses;
949950
llvm::append_range(ImplicitOps, II->ImplicitDefs);
950951
if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
951952
ImplicitLists.push_back(ImplicitOps);
@@ -1175,8 +1176,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
11751176
}
11761177

11771178
void InstrInfoEmitter::emitRecord(
1178-
const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo,
1179-
std::map<std::vector<Record *>, unsigned> &EmittedLists,
1179+
const CodeGenInstruction &Inst, unsigned Num, const Record *InstrInfo,
1180+
std::map<std::vector<const Record *>, unsigned> &EmittedLists,
11801181
const OperandInfoMapTy &OperandInfoMap, raw_ostream &OS) {
11811182
int MinOperands = 0;
11821183
if (!Inst.Operands.empty())
@@ -1195,11 +1196,11 @@ void InstrInfoEmitter::emitRecord(
11951196
<< Inst.TheDef->getValueAsInt("Size") << ",\t"
11961197
<< SchedModels.getSchedClassIdx(Inst) << ",\t";
11971198

1198-
CodeGenTarget &Target = CDP.getTargetInfo();
1199+
const CodeGenTarget &Target = CDP.getTargetInfo();
11991200

12001201
// Emit the implicit use/def list...
12011202
OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
1202-
std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
1203+
std::vector<const Record *> ImplicitOps = Inst.ImplicitUses;
12031204
llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
12041205
OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
12051206
<< ",\t";

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